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42 条记录 (耗时 0.025 秒)

    Method of implanting using a shadow effect
    21.
    发明授权
    Method of implanting using a shadow effect 有权
    使用阴影效果进行植入的方法

    公开(公告)号：US07767562B2

    公开(公告)日：2010-08-03

    申请号：US11235330

    申请日：2005-09-26

    申请人： Helmut Horst Tews ,  Jochen Beintner

    发明人： Helmut Horst Tews ,  Jochen Beintner

    IPC分类号： H01L21/425

    CPC分类号： H01L21/823462 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/2822 ,  H01L21/823481 ,  H01L27/0629 ,  H01L27/10873 ,  Y10S438/981

    摘要： A semiconductor body has a first portion, a second portion, and an active area located between the first portion and the second portion. The first portion and the second portion are a shallow trench isolation region having an exposed surface extending above the surface of the active area. A first ion implantation is performed at a first angle such that a first shaded area defined by the exposed surface of the first portion and the first angle is exposed to fewer ions than a first unshaded area. A second ion implantation is performed at a second angle such that a second shaded area defined by the exposed surface of the second portion and the second angle is exposed to fewer ions than a second unshaded area.

    摘要翻译： 半导体本体具有位于第一部分和第二部分之间的第一部分，第二部分和有源区域。 第一部分和第二部分是具有在有源区域的表面上方延伸的暴露表面的浅沟槽隔离区域。 以第一角度执行第一离子注入，使得由第一部分的暴露表面限定的第一阴影区域和第一角度暴露于比第一未阴影区域更少的离子。 以第二角度执行第二离子注入，使得由第二部分的暴露表面限定的第二阴影区域和第二角度暴露于比第二未阴影区域更少的离子。

    Control of oxide thickness in vertical transistor structures
    23.
    发明授权
    Control of oxide thickness in vertical transistor structures 有权
    垂直晶体管结构中氧化物厚度的控制

    公开(公告)号：US06372567B1

    公开(公告)日：2002-04-16

    申请号：US09553708

    申请日：2000-04-20

    申请人： Helmut Horst Tews ,  Brian S. Lee ,  Ulrike Gruening

    发明人： Helmut Horst Tews ,  Brian S. Lee ,  Ulrike Gruening

    IPC分类号： H01L218238

    CPC分类号： H01L21/28211 ,  H01L21/2236 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/2822 ,  H01L21/28238 ,  H01L27/10864 ,  H01L27/10873 ,  H01L29/045

    摘要： Improved process for preparing vertical transistor structures in DRAMs, in which the trench top oxide separates the bottom storage capacitor from the switching transistor, and in which the upper part of the trench contains the vertical transistor at its side wall, to obtain homogeneous gate oxidation at all different crystal planes inside the trench so that homogeneous thickness is independent of crystal orientation comprising: a) subjecting a wafer trench side wall to ion bombardment for a period sufficient to generate an amorphous layer of oxide side wall; and b) heating the wafer resulting from step (a) in an oxidizing atmosphere to cause oxidation and recrystallization of the amorphous layer.

    摘要翻译： 在DRAM中制备垂直晶体管结构的改进方法，其中沟槽顶部氧化物将底部存储电容器与开关晶体管分离，并且其中沟槽的上部在其侧壁处包含垂直晶体管，以获得均匀的栅极氧化 沟槽内的所有不同的晶面，使得均匀的厚度与晶体取向无关，包括：a）使晶片沟槽侧壁进行离子轰击足以产生氧化物侧壁的非晶层的时间; 和b）在氧化气氛中加热由步骤（a）得到的晶片，以引起非晶层的氧化和重结晶。

    Process flow for sacrificial collar with polysilicon void
    25.
    发明授权
    Process flow for sacrificial collar with polysilicon void 有权
    具有多晶硅空隙的牺牲环的工艺流程

    公开(公告)号：US06544855B1

    公开(公告)日：2003-04-08

    申请号：US10041779

    申请日：2001-10-19

    申请人： Helmut Horst Tews ,  Rolf Weis ,  Irene Lennox McStay

    发明人： Helmut Horst Tews ,  Rolf Weis ,  Irene Lennox McStay

    IPC分类号： H01L2120

    CPC分类号： H01L27/1087 ,  H01L27/10867

    摘要： A process for forming a sacrificial collar on the top portion of a deep trench (114) of a semiconductor wafer (100). A nitride layer (116) is deposited within the trenches (114). A semiconductor material layer (120) is deposited over the nitride layer (116) and is etched back to a predetermined height (A) below the substrate 112 top surface. A semiconductor material plug (132) is formed at the top surface of the recessed semiconductor material layer (120), leaving a void (133) in the bottom of each trench (114). An oxide layer (134) and nitride layer (136) are formed over the wafer (100) and trenches (116), and the semiconductor material plug (132) and semiconductor material layer (120) are removed from the bottom of the trenches (116).

    摘要翻译： 一种用于在半导体晶片（100）的深沟槽（114）的顶部上形成牺牲套环的工艺。 氮化物层（116）沉积在沟槽（114）内。 半导体材料层（120）沉积在氮化物层（116）上并且被回蚀刻到衬底112顶表面下方的预定高度（A）。 半导体材料插塞（132）形成在凹陷半导体材料层（120）的顶表面处，在每个沟槽（114）的底部留下空隙（133）。 在晶片（100）和沟槽（116）之上形成氧化物层（134）和氮化物层（136），半导体材料插塞（132）和半导体材料层（120）从沟槽的底部 116）。

    Reduction of orientation dependent oxidation for vertical sidewalls of semiconductor substrates
    26.
    发明授权
    Reduction of orientation dependent oxidation for vertical sidewalls of semiconductor substrates 失效
    减少半导体衬底的垂直侧壁的取向依赖氧化

    公开(公告)号：US06362040B1

    公开(公告)日：2002-03-26

    申请号：US09501502

    申请日：2000-02-09

    申请人： Helmut Horst Tews ,  Brian S. Lee ,  Ulrike Gruening ,  Raj Jammy ,  John Faltermeier

    发明人： Helmut Horst Tews ,  Brian S. Lee ,  Ulrike Gruening ,  Raj Jammy ,  John Faltermeier

    IPC分类号： H01L218242

    CPC分类号： H01L27/10864 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02299 ,  H01L21/31662 ,  H01L27/10876

    摘要： A method for growing a dielectric layer on a substrate, in accordance with the present invention, includes the steps of providing a substrate having at least two crystallographic planes which experience different dielectric layer growth rates due to the at least two crystallographic planes. A first dielectric layer is grown on the at least two crystallographic planes such that the first dielectric layer has a first thickness on a first crystallographic plane and a second thickness on a second crystallographic plane. The first thickness is thicker than the second thickness for the first dielectric layer. Dopants are implanted through the first dielectric layer. A greater number of dopants are implanted in the substrate through the second thickness than through the first thickness of the first dielectric layer. The first dielectric layer is then removed. A second dielectric layer is grown at a same location as the removed first dielectric layer. The second dielectric layer has a first thickness on a first crystallographic plane and a second thickness on a second crystallographic plane. The first thickness and the second thickness of the second dielectric layer are closer in thickness than the first thickness and the second thickness of the first dielectric layer due to the implantation of the dopants.

    摘要翻译： 根据本发明的用于在衬底上生长电介质层的方法包括以下步骤：提供具有至少两个结晶面的衬底，所述晶体面由于至少两个晶面而具有不同的介电层生长速率。 在至少两个晶面上生长第一介电层，使得第一介电层在第一结晶平面上具有第一厚度，在第二结晶平面上具有第二厚度。 第一厚度比第一电介质层的第二厚度厚。 通过第一介电层注入掺杂剂。 通过第二厚度将更多数量的掺杂剂注入到衬底中，而不是通过第一介电层的第一厚度。 然后去除第一介电层。 在与去除的第一介电层相同的位置处生长第二介电层。 第二电介质层在第一结晶平面上具有第一厚度，在第二结晶平面上具有第二厚度。 由于掺杂剂的注入，第二介电层的第一厚度和第二厚度比第一厚度和第一介电层的第二厚度更厚。

    Method of forming self-limiting polysilicon LOCOS for DRAM cell
    28.
    发明授权
    Method of forming self-limiting polysilicon LOCOS for DRAM cell 失效
    DRAM单元形成自限多晶硅LOCOS的方法

    公开(公告)号：US06309924B1

    公开(公告)日：2001-10-30

    申请号：US09585898

    申请日：2000-06-02

    申请人： Ramachandra Divakaruni ,  Jack Allan Mandelman ,  Irene Lennox McStay ,  Larry A. Nesbit ,  Carl John Radens ,  Helmut Horst Tews

    发明人： Ramachandra Divakaruni ,  Jack Allan Mandelman ,  Irene Lennox McStay ,  Larry A. Nesbit ,  Carl John Radens ,  Helmut Horst Tews

    IPC分类号： H01L218242

    CPC分类号： H01L27/10861 ,  H01L27/10867

    摘要： A method of forming relatively thin uniform insulating collar in the storage trench of a storage trench DRAM cell. A DRAM trench is first formed in a silicon substrate. Then, a nitride liner is deposited on the silicon trench walls. The nitride liner may be deposited directly on the silicon walls or on an underlying oxide layer. A layer of amorphous silicon is then deposited over the nitride liner. A silicon nitride layer is deposited on the oxidized surface of the amorphous silicon. A resist is formed in the lower portion of the trench, and the exposed silicon nitride layer on top of the amorphous silicon is removed, leaving the upper portion of the amorphous silicon layer exposed. The upper portion of the layer of amorphous silicon is then oxidized so as to form a relatively thin, uniform collar along the entire circumference of the trench. The nitride liner underlying the amorphous silicon layer enhances the thickness uniformity of the amorphous silicon layer and thereby the uniformity of the resulting oxide collar. The nitride liner also acts to limit lateral oxidation of the silicon trench walls during oxidation of the amorphous silicon layer. The nitride liner underlying the collar is also effective in cell operation to control the cell charge at the collar-substrate interface.

    摘要翻译： 一种在存储沟槽DRAM单元的存储沟槽中形成相对薄的均匀绝缘环的方法。 首先在硅衬底中形成DRAM沟槽。 然后，氮化物衬垫沉积在硅沟槽壁上。 氮化物衬垫可以直接沉积在硅壁上或下面的氧化物层上。 然后将一层非晶硅沉积在氮化物衬垫上。 在非晶硅的氧化表面上沉积氮化硅层。 在沟槽的下部形成抗蚀剂，去除在非晶硅顶部的暴露的氮化硅层，留下非晶硅层的上部。 然后，非晶硅层的上部被氧化，以便沿沟槽的整个圆周形成相对较薄的均匀的环。 非晶硅层下面的氮化物衬垫增强了非晶硅层的厚度均匀性，从而提高了所得氧化物环的均匀性。 氮化物衬垫还用于在非晶硅层的氧化期间限制硅沟槽壁的横向氧化。 在套环下面的氮化物衬垫在电池操作中也有效地控制在衬套 - 衬底界面处的电池电荷。

    Process for improving the thickness uniformity of a thin layer in semiconductor wafer fabrication
    29.
    发明授权
    Process for improving the thickness uniformity of a thin layer in semiconductor wafer fabrication 有权
    用于改善半导体晶片制造中的薄层的厚度均匀性的方法

    公开(公告)号：US06235651B1

    公开(公告)日：2001-05-22

    申请号：US09395952

    申请日：1999-09-14

    申请人： Martin Schrems ,  Helmut Horst Tews

    发明人： Martin Schrems ,  Helmut Horst Tews

    IPC分类号： H01L2131

    CPC分类号： H01L21/02238 ,  H01L21/02255 ,  H01L21/31662

    摘要： A two-step progressive thermal oxidation process is provided to improve the thickness uniformity of a thin oxide layer in semiconductor wafer fabrication. A semiconductor wafer, e.g., of silicon, with a surface subject to formation of an oxide layer thereon but which is substantially oxide layer-free, is loaded, e.g., at room temperature, into an oxidation furnace maintained at a low loading temperature, e.g., of 400-600° C., and the wafer temperature is adjusted to a low oxidizing temperature, e.g., of 400-600° C., all while the wafer is under an inert, e.g., nitrogen, atmosphere. The wafer is then subjected to initial oxidation, e.g., in dry oxygen, at the low oxidizing temperature to form a uniform initial thickness oxide, e.g., silicon dioxide, layer, e.g., of up to 10 angstroms, on the surface, after which the furnace temperature is increased to a high oxidizing temperature, e.g., of 700-1200° C., while the wafer is under an inert atmosphere. The wafer is next subjected to final oxidation, e.g., in oxygen and/or water vapor, at the high oxidizing temperature to increase uniformly the oxide layer to a selective final thickness, e.g., of 20-100 angstroms, whereupon the resultant uniform final thickness oxide layer-containing wafer is recovered from the furnace.

    摘要翻译： 提供了两步逐步热氧化工艺以改善半导体晶片制造中薄氧化物层的厚度均匀性。 诸如硅的半导体晶片，具有在其上形成氧化物层但基本上不含氧化物层的表面，例如在室温下被加载到维持在低负载温度的氧化炉中，例如 ，400-600℃，并且将晶片温度调节至低氧化温度，例如400-600℃，同时晶片处于惰性，例如氮气氛下。 然后将晶片在低氧化温度下进行初始氧化，例如在干燥的氧气中，以在表面上形成均匀的初始厚度氧化物，例如二氧化硅，例如至多10埃的层，之后 炉温升高到高的氧化温度，例如700-1200℃，同时晶片处于惰性气氛。 接着在高氧化温度下将晶片进行最终氧化，例如在氧气和/或水蒸气中，以将氧化物层均匀地增加至选择性最终厚度，例如20-100埃，由此得到均匀的最终厚度 从炉中回收含氧化物层的晶片。

    Strained semiconductor device and method of making the same
    30.
    发明授权
    Strained semiconductor device and method of making the same 有权
    应变半导体器件及其制造方法

    公开(公告)号：US08003470B2

    公开(公告)日：2011-08-23

    申请号：US11224825

    申请日：2005-09-13

    申请人： Helmut Horst Tews ,  Andre Schenk

    发明人： Helmut Horst Tews ,  Andre Schenk

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/66477 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7834

    摘要： In a method for forming a semiconductor device, a gate electrode is formed over a semiconductor body (e.g., bulk silicon substrate or SOI layer). The gate electrode is electrically insulated from the semiconductor body. A first sidewall spacer is formed along a sidewall of the gate electrode. A sacrificial sidewall spacer is formed adjacent the first sidewall spacer. The sacrificial sidewall spacer and the first sidewall spacer overlying the semiconductor body. A planarization layer is formed over the semiconductor body such that a portion of the planarization layer is adjacent the sacrificial sidewall spacer. The sacrificial sidewall spacer can then be removed and a recess etched in the semiconductor body. The recess is substantially aligned between the first sidewall spacer and the portion of the planarization layer. A semiconductor material (e.g., SiGe or SiC) can then be formed in the recess.

    摘要翻译： 在形成半导体器件的方法中，在半导体本体（例如体硅衬底或SOI层）上形成栅电极。 栅电极与半导体本体电绝缘。 沿着栅电极的侧壁形成第一侧壁间隔物。 邻近第一侧壁间隔件形成牺牲侧壁间隔物。 牺牲侧壁间隔件和覆盖半导体本体的第一侧壁间隔件。 平坦化层形成在半导体本体上，使得平坦化层的一部分与牺牲侧壁间隔物相邻。 然后可以去除牺牲侧壁间隔物并在半导体本体中蚀刻凹陷。 所述凹部基本上在所述第一侧壁间隔物和所述平坦化层的所述部分之间对准。 然后可以在凹部中形成半导体材料（例如，SiGe或SiC）。