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    Block erasable nonvolatile memory device
    23.
    发明授权
    Block erasable nonvolatile memory device 失效
    块可擦除非易失性存储器件

    公开(公告)号：US5371702A

    公开(公告)日：1994-12-06

    申请号：US27489

    申请日：1993-03-05

    申请人： Hiroto Nakai ,  Hideo Kato ,  Kaoru Tokushige ,  Masamichi Asano ,  Kazuhisa Kanazawa ,  Toshio Yamamura

    发明人： Hiroto Nakai ,  Hideo Kato ,  Kaoru Tokushige ,  Masamichi Asano ,  Kazuhisa Kanazawa ,  Toshio Yamamura

    IPC分类号： G11C16/16 ,  G11C11/34 ,  G11C7/00

    CPC分类号： G11C16/16

    摘要： In response to a plurality of address signal input from the outside in sequence, an erase information inputting section controls an erase information holding section corresponding to the batch erase block to be erased so as to hold an erase information data. By repeating this operation in sequence, the erase information data are stored in the erase information holding sections corresponding to the plural batch erase blocks to be erased. Successively, on the basis of the erase information data stored in the erase information holding sections, block erasing sections are activated to erase all the nonvolatile memory cells of each of the corresponding blocks where the erase information data are held. As a result, the erasure operation is achieved for all the batch erase blocks corresponding to the erase information holding sections in each of which the erase information data is held, so that a plurality of batch erase blocks can be erased simulataneously, thus reducing the erasure time, as compared with the prior art memory device.

    摘要翻译： 响应于从外部依次输入的多个地址信号，擦除信息输入部分控制与待擦除的批量擦除块相对应的擦除信息保持部分，以便保存擦除信息数据。 通过依次重复该操作，擦除信息数据被存储在与要擦除的多批擦除块相对应的擦除信息保持部分中。 接着，基于存储在擦除信息保持部中的擦除信息数据，块消除部分被激活，以擦除保持擦除信息数据的每个相应块的所有非易失性存储器单元。 结果，对于与保持擦除信息数据的擦除信息保持部分相对应的所有批量擦除块实现擦除操作，使得可以同时擦除多个批量擦除块，从而减少擦除 与现有技术的存储器件相比。

    Non-volatile semiconductor memory device using successively longer write pulses
    27.
    发明授权
    Non-volatile semiconductor memory device using successively longer write pulses 失效
    使用连续更长写入脉冲的非易失性半导体存储器件

    公开(公告)号：US5436913A

    公开(公告)日：1995-07-25

    申请号：US069911

    申请日：1993-06-01

    申请人： Toshio Yamamura ,  Hiroto Nakai ,  Hideo Kato ,  Kaoru Tokushige ,  Masamichi Asano

    发明人： Toshio Yamamura ,  Hiroto Nakai ,  Hideo Kato ,  Kaoru Tokushige ,  Masamichi Asano

    IPC分类号： G11C16/34 ,  G06F11/00

    CPC分类号： G11C16/3459 ,  G11C16/3454

    摘要： A non-volatile semiconductor memory device has writing part (203, 205, 209) for writing data in a non-volatile memory cell in response to a write pulse, readout part (419) for reading out data stored in the memory cell, and verification part (207, 210; 417) for verifying to ensure that normal writing has been completed by reading data from the memory cell after each writing. The device repeats writings unless a normal writing can be confirmed by the verification part. At this time, the writing part can vary writing time and in a part of a sequence of repeating writing unless a normal writing can be confirmed, it sets writing time longer for the next writing action than that for one writing action. Since this setting is performed according to constant multiplication, constant increment, or constant multiplication of accumulated value, necessary time for obtaining normal data write can be reduced.

    摘要翻译： 非挥发性半导体存储器件具有写入部分（203,205,209），用于响应写入脉冲在非易失性存储单元中写入数据，用于读出存储在存储器单元中的数据的读出部分（419）以及 验证部件（207,210; 417），用于通过在每次写入之后从存储器单元读取数据来验证以确保正常写入已经完成。 设备重复写入，除非验证部分可以确认正常写入。 此时，写入部分可以改变写入时间，并且在重复写入序列的一部分中，除非正常写入可以被确认，否则为下一个写入动作设置比一个写入动作的写入时间更长的时间。 由于根据常数乘法，常数增量或累积值的常数乘法执行该设置，因此可以减少获得正常数据写入所需的时间。

    Non-volatile semiconductor memory device
    28.
    发明授权
    Non-volatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US5428569A

    公开(公告)日：1995-06-27

    申请号：US38985

    申请日：1993-03-29

    申请人： Hideo Kato ,  Hiroto Nakai ,  Masamichi Asano ,  Kaoru Tokushige

    发明人： Hideo Kato ,  Hiroto Nakai ,  Masamichi Asano ,  Kaoru Tokushige

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/12 ,  G11C16/16 ,  G11C29/00 ,  G11C29/12 ,  G11C29/24 ,  G11C29/50 ,  G11C29/52 ,  G11C7/00

    CPC分类号： G11C16/12 ,  G11C16/16 ,  G11C29/50 ,  G11C29/52 ,  G11C16/04

    摘要： A non-volatile semiconductor memory device comprises: a plurality of memory cells for electrically rewriting data; a programming and erasing section for executing data writing programs and data erasing operation for the memory cells; a verifying section for discriminating whether a data is written in or erased from one of the memory cells properly whenever data are written to or erased from the memory cells; and an automatic control section for enabling the programming and erasing section to execute the data writing program and erasing operation again whenever the verifying section discriminates that data is not properly written to or erased from one of the memory cells, the data writing program or erasing operation being executed repeatedly by the number of times less than a user-defined maximum program execution or erasing operation number applied externally from the outside of the memory device. Further, the number of data writing and erasing operations can be outputted to the outside of the chip. Therefore, it is possible to optimize the limit of the data writing operation according to the chip samples and to detect the deterioration status of he chip externally from the chip. The reliability of a system using the memory devices can be improved, and further the chip exchange timing can be indicated to the user.

    摘要翻译： 非挥发性半导体存储器件包括：用于电重写数据的多个存储单元; 用于对存储单元执行数据写入程序和数据擦除操作的编程和擦除部分; 一个验证部分，用于鉴别每当数据被从存储器单元写入或擦除时，正确地从一个存储器单元写入数据或从其中擦除数据; 以及自动控制部分，用于使编程和擦除部分能够每当验证部分识别数据未被正确地从存储器单元之一写入或擦除时执行数据写入程序和擦除操作，数据写入程序或擦除操作 重复执行小于从存储装置的外部外部施加的用户定义的最大程序执行或擦除操作数的次数。 此外，可以将数据写入和擦除操作的数量输出到芯片的外部。 因此，可以根据芯片样本优化数据写入操作的限制，并且从芯片外部检测芯片的劣化状态。 可以提高使用存储器件的系统的可靠性，并且可以向用户指示芯片交换定时。

    Semiconductor memory device
    29.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5297029A

    公开(公告)日：1994-03-22

    申请号：US993109

    申请日：1992-12-18

    申请人： Hiroto Nakai ,  Hideo Kato ,  Kaoru Tokushige ,  Masamichi Asano

    发明人： Hiroto Nakai ,  Hideo Kato ,  Kaoru Tokushige ,  Masamichi Asano

    IPC分类号： G06F3/06 ,  G11C7/10 ,  G11C8/04 ,  G11C16/04 ,  G11C8/00

    CPC分类号： G06F3/0601 ,  G11C16/0483 ,  G11C7/103 ,  G11C8/04 ,  G06F2003/0694

    摘要： In reading data, data is transferred to data registers starting from a data read start address to the last address at a row (page), and data at the next page is transferred to the data registers starting from a start address to the last address at that page. These operations are repeated. In writing data from an intermediate address of a page, predetermined data is written in data registers not having write data. It is possible to read data at consecutive pages from a first predetermined column address to the page last address, and to read data at consecutive pages from a second predetermined column address to the page last address. For the data structure having a first data structure and a second data structure, it is possible to continuously read a set of data having both the first and second data structures and a set of data having only the second data structure, improving the efficiency of a system using a semiconductor memory device.

    摘要翻译： 在读取数据时，将数据从数据读取开始地址开始传输到一行（页面）的最后一个地址，将数据从数据寄存器传送到数据寄存器，从起始地址开始到最后一个地址 那个页面。 重复这些操作。 在从页面的中间地址写入数据时，将预定数据写入不具有写入数据的数据寄存器中。 可以在从第一预定列地址到页面最后地址的连续页面读取数据，并且从连续页面将数据从第二预定列地址读取到页面最后地址。 对于具有第一数据结构和第二数据结构的数据结构，可以连续读取具有第一和第二数据结构的数据集合和仅具有第二数据结构的一组数据，从而提高 系统使用半导体存储器件。