公开(公告)号：US4903238A

公开(公告)日：1990-02-20

申请号：US201787

申请日：1988-06-02

申请人： Hideshi Miyatake ,  Masaki Kumanoya ,  Katsumi Dosaka

发明人： Hideshi Miyatake ,  Masaki Kumanoya ,  Katsumi Dosaka

IPC分类号： G11C11/41 ,  G11C5/14 ,  G11C11/409 ,  G11C11/419

CPC分类号： G11C11/419 ,  G11C5/14

摘要： A semiconductor memory device such as a static RAM (Random Access Memory) device comprises a ground connection circuit of n channel field effect transistors connected between two I/O lines and the ground. The precharge circuit for precharging and the ground connection circuit both operate in response to the signal which is in synchronization with an externally applied external chip select signal. Therefore, the access delay derived from the fluctuation of the supply voltage generated before the change of the external chip select signal can be prevented.

摘要翻译： 诸如静态RAM（随机存取存储器）装置的半导体存储器件包括连接在两个I / O线和地之间的n沟道场效应晶体管的接地连接电路。 用于预充电的预充电电路和接地连接电路都响应于与外部施加的外部芯片选择信号同步的信号而工作。 因此，可以防止在外部芯片选择信号改变之前产生的电源电压的波动导致的访问延迟。

公开(公告)号：US4934826A

公开(公告)日：1990-06-19

申请号：US211548

申请日：1988-06-24

申请人： Hideshi Miyatake ,  Hiroyuki Yamasaki ,  Masaki Shimoda ,  Kazuhiro Tsukamoto

发明人： Hideshi Miyatake ,  Hiroyuki Yamasaki ,  Masaki Shimoda ,  Kazuhiro Tsukamoto

IPC分类号： G11C11/406 ,  G11C11/408 ,  G11C11/409

CPC分类号： G11C11/409 ,  G11C11/406 ,  G11C11/408

摘要： A word line driving signal generating circuit and a sense amplifier activating signal generating circuit are provided for every partitioned memory cell array. When the levels of an external RAS signal and an external CAS signal have a predetermined relation and an external RNC signal remains at a predetermined potential or more, a refresh operation is started. A refresh address is generated from a refresh address counter in a sense restore control circuit. All of the memory cell arrays are simultaneously refreshed in response to the address. On this occasion, an operation for selecting a column by a column decoder provided in each of the memory cell arrays is inhibited. In the case in which an input of the external RNC signal is not prepared, when the levels of the external RAS signal and the external CAS signal have a predetermined relation and this state is held in a predetermined time period or more, the same refresh operation as described above is started.

摘要翻译： 为每个分区存储单元阵列提供字线驱动信号发生电路和读出放大器激活信号产生电路。 当外部RAS信号和外部CAS信号的电平具有预定关系并且外部RNC信号保持在预定电位或更大时，开始刷新操作。 从感测恢复控制电路中的刷新地址计数器产生刷新地址。 响应于地址，所有的存储单元阵列被同时刷新。 在这种情况下，禁止通过设置在每个存储单元阵列中的列解码器来选择列的操作。 在没有准备外部RNC信号的输入的情况下，当外部RAS信号和外部CAS信号的电平具有预定关系并且该状态保持在预定时间段或更长时间时，相同的刷新操作 如上所述开始。

公开(公告)号：US4982367A

公开(公告)日：1991-01-01

申请号：US192575

申请日：1988-05-11

申请人： Hideshi Miyatake

发明人： Hideshi Miyatake

IPC分类号： G11C11/409 ,  G11C7/12 ,  G11C11/401 ,  G11C11/4094

CPC分类号： G11C11/4094 ,  G11C7/12

摘要： A DRAM comprises equalizing capacitance for equalizing the difference between a potential on a bit line to which a selected memory cell is connected and a potential on a reference bit line paired with the bit line when the selected memory cell stores "H" information and that when the selected memory cell stores "L" information, before sensing operation is started. The amplitude of a potential on a selected word line is at an operating power-supply voltage Vcc level of the DRAM.

摘要翻译： DRAM包括均衡电容，用于在所选择的存储单元存储“H”信息时均衡与连接选定存储单元的位线上的电位和与位线配对的参考位线上的电位之间的差值，以及当 在开始感测操作之前，所选存储单元存储“L”信息。 所选字线上的电位的幅度处于DRAM的工作电源电压Vcc电平。

公开(公告)号：US4658379A

公开(公告)日：1987-04-14

申请号：US666380

申请日：1984-10-30

申请人： Kazuyasu Fujishima ,  Kazuhiro Shimotori ,  Hideyuki Ozaki ,  Hideshi Miyatake ,  Masahiro Tomisato

发明人： Kazuyasu Fujishima ,  Kazuhiro Shimotori ,  Hideyuki Ozaki ,  Hideshi Miyatake ,  Masahiro Tomisato

IPC分类号： G11C8/10 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/787 ,  G11C8/10

摘要： A semiconductor memory device with a laser programmable redundancy circuit, which includes: a plurality of decoders for selecting a row or column of the memory; at least one spare decoder which is selected instead of a decoder connected to a faulty memory cell; a link element inserted in series with the precharging transistor and connected between the power supply and the decoder output line; a signal generator which generates a non-selection signal for making the object decoder unselected only when a spare decoder is selected, the signal generator being provided in the spare decoder; and a transistor, having a gate to which the non-selection signal is input, with the drain and the source thereof being connected to the decoder output and ground, respectively, the transistor being provided in the decoder.

摘要翻译： 一种具有激光可编程冗余电路的半导体存储器件，包括：多个解码器，用于选择存储器的行或列; 选择代替连接到故障存储器单元的解码器的至少一个备用解码器; 与预充电晶体管串联插入并连接在电源和解码器输出线之间的连接元件; 信号发生器，其仅在选择了备用解码器时产生用于使对象解码器未选择的非选择信号，所述信号发生器设置在所述备用解码器中; 以及晶体管，其具有输入非选择信号的栅极，漏极和源极分别连接到解码器输出和接地，晶体管分别设置在解码器中。

公开(公告)号：US4586167A

公开(公告)日：1986-04-29

申请号：US568138

申请日：1984-01-04

申请人： Kazuyasu Fujishima ,  Kazuhiro Shimotori ,  Hideyuki Ozaki ,  Hideshi Miyatake

发明人： Kazuyasu Fujishima ,  Kazuhiro Shimotori ,  Hideyuki Ozaki ,  Hideshi Miyatake

IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C8/18 ,  G11C13/00

CPC分类号： G11C7/1045 ,  G11C7/22 ,  G11C8/18

摘要： Disclosed is a semiconductor memory device which is operable in a selected one of page mode and nibble mode, depending upon the length of time in which an external column address strobe signal stays at a specific level. The semiconductor memory device comprises a circuit for discriminating the length of time where the external column address strobe signal is at a specific level with a predetermined period of time. Data is outputted in page mode in response to one of results of such discrimination and in nibble mode in response to the other result of the discrimination. The discriminating circuit may comprise a second internal column address strobe signal generator and a delay circuit. The second internal column address strobe signal generator includes a NAND circuit at its first stage, and the delay circuit is designed to have different delay times at the building-up and downward edges of an input signal applied thereto. The output of the discriminator is used to operate and reset an output circuit whereby one of the output modes is selected.

摘要翻译： 公开了根据外部列地址选通信号保持在特定级别的时间长度，可以在页模式和半字节模式中选择的一个中操作的半导体存储器件。 半导体存储器件包括用于在预定时间段内鉴别外部列地址选通信号处于特定电平的时间长度的电路。 响应于这种歧视的结果之一，以页面模式输出数据，并且响应于歧视的另一结果，以半字节模式输出数据。 识别电路可以包括第二内部列地址选通信号发生器和延迟电路。 第二内部列地址选通信号发生器包括在其第一级的NAND电路，并且延迟电路被设计为在施加到其的输入信号的建立和向下边缘处具有不同的延迟时间。 鉴别器的输出用于操作和复位输出电路，由此选择一个输出模式。

公开(公告)号：US4980864A

公开(公告)日：1990-12-25

申请号：US282142

申请日：1988-12-09

申请人： Ryoji Fukuhama ,  Hideshi Miyatake

发明人： Ryoji Fukuhama ,  Hideshi Miyatake

IPC分类号： G11C11/401 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4097

CPC分类号： G11C11/4097 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096

摘要： A semiconductor dynamic random access memory is provided comprising bit line pairs divided into groups and sense amplifiers, one for each bit line pair group provided on one side of the bit line pairs in a line. When a word line is selected, only one bit line pair is released from a precharge.equalize state to be connected to a corresponding sense amplifier in each bit line pair group in accordance with address information of the word line. Memory cells are arranged such that only one memory cell is connected to the selected word line in each bit line pair group.

摘要翻译： 提供了一种半导体动态随机存取存储器，其包括被分成组和读出放大器的位线对，一行位于一行中的位线对的一侧上的位线对组。 当选择字线时，根据字线的地址信息，只有一个位线对从预充电状态被释放以连接到每个位线对组中的对应读出放大器。 存储单元被布置成使得在每个位线对组中只有一个存储单元连接到所选择的字线。

公开(公告)号：US4694432A

公开(公告)日：1987-09-15

申请号：US709409

申请日：1985-03-06

申请人： Hideshi Miyatake ,  Kazuyasu Fujishima ,  Kazuhiro Shimotori

发明人： Hideshi Miyatake ,  Kazuyasu Fujishima ,  Kazuhiro Shimotori

IPC分类号： G11C11/401 ,  G11C8/08 ,  G11C29/00 ,  G11C29/04 ,  G11C13/00

CPC分类号： G11C29/787 ,  G11C8/08

摘要： A semiconductor memory device comprises a plurality of row decoder circuits connected with word lines for selecting memory cells. The row decoder circuits include normal row decoder circuits and spare row decoder circuits which can be selected in place of a normal row decoder circuit in case where a fault occurs in a memory cell selected by a word line connected to the normal row decoder circuit. An RAS signal (precharge signal) is applied to an output line (12) of a normal row decoder circuit through a precharge bus (31). A link element (11p) is inserted in the precharge bus (31). The link element (11p) is an element which can be melted by a laser beam, whereby the normal row decoder circuit associated is maintained in a non-selective state. A clamp circuit (14) is also connected to the output line (12). The clamp circuit (14) is a circuit for maintaining the output line (12) at a prescribed low level when the link element (11p) is melted and the associated decoder circuit is brought into a non-selective state.

摘要翻译： 半导体存储器件包括与用于选择存储器单元的字线连接的多个行解码器电路。 行解码器电路包括普通行解码器电路和备用行解码器电路，其可以在由连接到正常行解码器电路的字线选择的存储单元中发生故障的情况下代替普通行解码器电路。 通过预充电总线（31）将正常行解码器电路的输入线（12）上的上拉和下拉信号（预充电信号）施加到正常行解码器电路。 连接元件（11p）插入预充电总线（31）中。 连接元件（11p）是可以被激光束熔化的元件，由此相关联的正常行解码器电路保持在非选择状态。 钳位电路（14）也连接到输出线（12）。 钳位电路（14）是当连接元件（11p）熔化并且相关联的解码器电路处于非选择状态时，用于将输出线（12）保持在规定的低电平的电路。

公开(公告)号：US4641286A

公开(公告)日：1987-02-03

申请号：US581000

申请日：1984-02-16

申请人： Kazuhiro Shimotori ,  Kazuyasu Fujishima ,  Hideyuki Ozaki ,  Hideshi Miyatake

发明人： Kazuhiro Shimotori ,  Kazuyasu Fujishima ,  Hideyuki Ozaki ,  Hideshi Miyatake

IPC分类号： G11C11/413 ,  G11C29/00 ,  G11C29/04 ,  G11C8/00

CPC分类号： G11C29/781

摘要： A semiconductor memory device in which at least a line decoder or a column decoder in multiplex form is provided to select one line selection signal or column selection signal. When the line decoder or column decoder is defective, or when the word line or bit line associated with the line decoder or column decoder involves a defective bit, the defective line decoder, column decoder, word line or bit line is inactivated. The inactivated line decoder or column decoder is replaced with an auxiliary line decoder or column decoder.

摘要翻译： 一种半导体存储器件，其中提供至少一个线路解码器或多路复用形式的列解码器以选择一个线选择信号或列选择信号。 当线路解码器或列解码器故障时，或者当与线路解码器或列解码器相关联的字线或位线涉及有缺陷的位时，故障线解码器，列解码器，字线或位线被停用。 灭活的行解码器或列解码器被替换为辅助线路解码器或列解码器。

公开(公告)号：US5020031A

公开(公告)日：1991-05-28

申请号：US444218

申请日：1989-12-01

申请人： Hideshi Miyatake

发明人： Hideshi Miyatake

IPC分类号： G11C11/409 ,  G11C11/4094 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： G11C11/4094

摘要： P-type sense amplifier and N-type sense amplifier are connected to each of bit lines in a pair of bit lines respectively. N-channel MOS transistor is connected to each of the bit lines between the P-type sense amplifier and the N-type sense amplifier, and normally turned on. Each of a plurality of memory cells is connected to any of the bit lines at the side of the N-type sense amplifier from the transistor. The power source potential generated by the P-type sense amplifier is dropped by the threshold voltage of the transistor and supplied to one of the bit liens to which the memory cells are connected. The ground potential generated by the N-type sense amplifier is supplied without changing the potential to other of the bit lines. If the threshold value of the transistors to constitute the memory cells is made equal to the threshold voltage of the transistors on the bit lines, intermediate potential between the potential as "H" level held in the memory cells and the potential as "L" level becomes equal to the precharge potential of the bit lines, thereby unbalance of the read-out voltages can be eliminated.

摘要翻译： P型读出放大器和N型读出放大器分别连接到一对位线中的每一位线。 N沟道MOS晶体管连接到P型读出放大器和N型读出放大器之间的每个位线，并且通常导通。 多个存储单元中的每一个都与晶体管连接在N型读出放大器一侧的位线中的任一位。 由P型读出放大器产生的电源电位下降到晶体管的阈值电压，并提供给存储单元连接到的位留置中的一个。 提供由N型读出放大器产生的接地电位而不改变其他位线的电位。 如果使构成存储单元的晶体管的阈值等于位线上的晶体管的阈值电压，则将存储单元中保持的“H”电位的电位和电位之间的中间电位设为“L”电平 变得等于位线的预充电电位，从而可以消除读出电压的不平衡。

公开(公告)号：US4575825A

公开(公告)日：1986-03-11

申请号：US568139

申请日：1984-01-04

申请人： Hideyuki Ozaki ,  Kazuhiro Shimotori ,  Hideshi Miyatake

发明人： Hideyuki Ozaki ,  Kazuhiro Shimotori ,  Hideshi Miyatake

IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C11/40

CPC分类号： G11C7/1045 ,  G11C7/22

摘要： Disclosed is a semiconductor memory device which is one of three types of semiconductor memory devices, one operable only in page mode, one operable only in nibble and one operable selectively in page mode or nibble mode, being obtained from a partially unconnected semiconductor memory device through alternations in a portions in wiring. The semiconductor memory device includes first and second internal column address strobe signal generator. The second internal column address strobe signal generator has at the first stage thereof a NAND circuit one of inputs to which determines the type of the semiconductor memory device depending on which of three kinds of signals is selected as the input. Selection of such an input is effected by an aluminum wiring process using a mask. Such selection of the input causes variation in the input response characteristics of the output of the second internal column address strobe signal generator, thus providing a desired response appropriate for the selected mode or modes.

摘要翻译： 公开了一种半导体存储器件，其是三种类型的半导体存储器件之一，一种只能以页模式操作，一种仅可半字节操作，一种可操作地以页模式或半字节模式操作，可从部分未连接的半导体存储器件通过 布线部分的交替。 半导体存储器件包括第一和第二内部列地址选通信号发生器。 第二内部列地址选通信号发生器在其第一级具有根据三种信号中的哪一种被选择作为输入的一个输入端的NAND电路，其确定半导体存储器件的类型。 这种输入的选择通过使用掩模的铝布线处理来实现。 输入的这种选择导致第二内部列地址选通信号发生器的输出的输入响应特性的变化，从而提供适合所选择的模式或方式的期望响应。