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    Semiconductor memory device with a laser programmable redundancy circuit
    1.
    发明授权
    Semiconductor memory device with a laser programmable redundancy circuit 失效
    具有激光可编程冗余电路的半导体存储器件

    公开(公告)号：US4658379A

    公开(公告)日：1987-04-14

    申请号：US666380

    申请日：1984-10-30

    申请人： Kazuyasu Fujishima ,  Kazuhiro Shimotori ,  Hideyuki Ozaki ,  Hideshi Miyatake ,  Masahiro Tomisato

    发明人： Kazuyasu Fujishima ,  Kazuhiro Shimotori ,  Hideyuki Ozaki ,  Hideshi Miyatake ,  Masahiro Tomisato

    IPC分类号： G11C8/10 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

    CPC分类号： G11C29/787 ,  G11C8/10

    摘要： A semiconductor memory device with a laser programmable redundancy circuit, which includes: a plurality of decoders for selecting a row or column of the memory; at least one spare decoder which is selected instead of a decoder connected to a faulty memory cell; a link element inserted in series with the precharging transistor and connected between the power supply and the decoder output line; a signal generator which generates a non-selection signal for making the object decoder unselected only when a spare decoder is selected, the signal generator being provided in the spare decoder; and a transistor, having a gate to which the non-selection signal is input, with the drain and the source thereof being connected to the decoder output and ground, respectively, the transistor being provided in the decoder.

    摘要翻译： 一种具有激光可编程冗余电路的半导体存储器件，包括：多个解码器，用于选择存储器的行或列; 选择代替连接到故障存储器单元的解码器的至少一个备用解码器; 与预充电晶体管串联插入并连接在电源和解码器输出线之间的连接元件; 信号发生器，其仅在选择了备用解码器时产生用于使对象解码器未选择的非选择信号，所述信号发生器设置在所述备用解码器中; 以及晶体管，其具有输入非选择信号的栅极，漏极和源极分别连接到解码器输出和接地，晶体管分别设置在解码器中。

    Semiconductor memory device
    2.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US4586167A

    公开(公告)日：1986-04-29

    申请号：US568138

    申请日：1984-01-04

    申请人： Kazuyasu Fujishima ,  Kazuhiro Shimotori ,  Hideyuki Ozaki ,  Hideshi Miyatake

    发明人： Kazuyasu Fujishima ,  Kazuhiro Shimotori ,  Hideyuki Ozaki ,  Hideshi Miyatake

    IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C8/18 ,  G11C13/00

    CPC分类号： G11C7/1045 ,  G11C7/22 ,  G11C8/18

    摘要： Disclosed is a semiconductor memory device which is operable in a selected one of page mode and nibble mode, depending upon the length of time in which an external column address strobe signal stays at a specific level. The semiconductor memory device comprises a circuit for discriminating the length of time where the external column address strobe signal is at a specific level with a predetermined period of time. Data is outputted in page mode in response to one of results of such discrimination and in nibble mode in response to the other result of the discrimination. The discriminating circuit may comprise a second internal column address strobe signal generator and a delay circuit. The second internal column address strobe signal generator includes a NAND circuit at its first stage, and the delay circuit is designed to have different delay times at the building-up and downward edges of an input signal applied thereto. The output of the discriminator is used to operate and reset an output circuit whereby one of the output modes is selected.

    摘要翻译： 公开了根据外部列地址选通信号保持在特定级别的时间长度，可以在页模式和半字节模式中选择的一个中操作的半导体存储器件。 半导体存储器件包括用于在预定时间段内鉴别外部列地址选通信号处于特定电平的时间长度的电路。 响应于这种歧视的结果之一，以页面模式输出数据，并且响应于歧视的另一结果，以半字节模式输出数据。 识别电路可以包括第二内部列地址选通信号发生器和延迟电路。 第二内部列地址选通信号发生器包括在其第一级的NAND电路，并且延迟电路被设计为在施加到其的输入信号的建立和向下边缘处具有不同的延迟时间。 鉴别器的输出用于操作和复位输出电路，由此选择一个输出模式。

    Auxiliary decoder for semiconductor memory device
    3.
    发明授权
    Auxiliary decoder for semiconductor memory device 失效
    半导体存储器件辅助解码器

    公开(公告)号：US4641286A

    公开(公告)日：1987-02-03

    申请号：US581000

    申请日：1984-02-16

    申请人： Kazuhiro Shimotori ,  Kazuyasu Fujishima ,  Hideyuki Ozaki ,  Hideshi Miyatake

    发明人： Kazuhiro Shimotori ,  Kazuyasu Fujishima ,  Hideyuki Ozaki ,  Hideshi Miyatake

    IPC分类号： G11C11/413 ,  G11C29/00 ,  G11C29/04 ,  G11C8/00

    CPC分类号： G11C29/781

    摘要： A semiconductor memory device in which at least a line decoder or a column decoder in multiplex form is provided to select one line selection signal or column selection signal. When the line decoder or column decoder is defective, or when the word line or bit line associated with the line decoder or column decoder involves a defective bit, the defective line decoder, column decoder, word line or bit line is inactivated. The inactivated line decoder or column decoder is replaced with an auxiliary line decoder or column decoder.

    摘要翻译： 一种半导体存储器件，其中提供至少一个线路解码器或多路复用形式的列解码器以选择一个线选择信号或列选择信号。 当线路解码器或列解码器故障时，或者当与线路解码器或列解码器相关联的字线或位线涉及有缺陷的位时，故障线解码器，列解码器，字线或位线被停用。 灭活的行解码器或列解码器被替换为辅助线路解码器或列解码器。

    Semiconductor memory device
    4.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US4694432A

    公开(公告)日：1987-09-15

    申请号：US709409

    申请日：1985-03-06

    申请人： Hideshi Miyatake ,  Kazuyasu Fujishima ,  Kazuhiro Shimotori

    发明人： Hideshi Miyatake ,  Kazuyasu Fujishima ,  Kazuhiro Shimotori

    IPC分类号： G11C11/401 ,  G11C8/08 ,  G11C29/00 ,  G11C29/04 ,  G11C13/00

    CPC分类号： G11C29/787 ,  G11C8/08

    摘要： A semiconductor memory device comprises a plurality of row decoder circuits connected with word lines for selecting memory cells. The row decoder circuits include normal row decoder circuits and spare row decoder circuits which can be selected in place of a normal row decoder circuit in case where a fault occurs in a memory cell selected by a word line connected to the normal row decoder circuit. An RAS signal (precharge signal) is applied to an output line (12) of a normal row decoder circuit through a precharge bus (31). A link element (11p) is inserted in the precharge bus (31). The link element (11p) is an element which can be melted by a laser beam, whereby the normal row decoder circuit associated is maintained in a non-selective state. A clamp circuit (14) is also connected to the output line (12). The clamp circuit (14) is a circuit for maintaining the output line (12) at a prescribed low level when the link element (11p) is melted and the associated decoder circuit is brought into a non-selective state.

    摘要翻译： 半导体存储器件包括与用于选择存储器单元的字线连接的多个行解码器电路。 行解码器电路包括普通行解码器电路和备用行解码器电路，其可以在由连接到正常行解码器电路的字线选择的存储单元中发生故障的情况下代替普通行解码器电路。 通过预充电总线（31）将正常行解码器电路的输入线（12）上的上拉和下拉信号（预充电信号）施加到正常行解码器电路。 连接元件（11p）插入预充电总线（31）中。 连接元件（11p）是可以被激光束熔化的元件，由此相关联的正常行解码器电路保持在非选择状态。 钳位电路（14）也连接到输出线（12）。 钳位电路（14）是当连接元件（11p）熔化并且相关联的解码器电路处于非选择状态时，用于将输出线（12）保持在规定的低电平的电路。

    Substrate bias generating circuit
    6.
    再颁专利
    Substrate bias generating circuit 失效
    基板偏压发生电路

    公开(公告)号：USRE35141E

    公开(公告)日：1996-01-09

    申请号：US142931

    申请日：1993-10-29

    申请人： Hideyuki Ozaki ,  Kazuyasu Fujishima ,  Kazuhiro Shimotori

    发明人： Hideyuki Ozaki ,  Kazuyasu Fujishima ,  Kazuhiro Shimotori

    IPC分类号： G11C11/417 ,  G05F3/20 ,  G11C5/14 ,  G11C11/34 ,  G11C11/4074 ,  G11C11/408 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10 ,  H03K19/094 ,  G11C7/00

    CPC分类号： G11C5/146 ,  G05F3/205 ,  G11C11/4074

    摘要： The disclosure described a substrate bias generating circuit in which an internal RAS (Row Address Strobe) signal and an internal CAS (Column Address Strobe) signal, both of which are synchronized with an external RAS signal and external CAS supplied from outside in addition to self-oscillator, activate circuits .[.comprising.]. .Iadd.including .Iaddend.capacitors and rectifying elements respectively so as to reduce wattage dissipation thereof during holding time of RAM and be obtained increased charge pump current during operation thereof.

    摘要翻译： 本公开描述了一种衬底偏置产生电路，其中内部＆上行＆行（行地址选通）信号和内部CAS（列地址选通）信号，两者都与外部＆上行＆R信号和从外部提供的外部＆upbar＆C同步 除了自振荡器之外，分别包括电容器和整流元件的电路[包括]，以便在RAM的保持时间期间降低功率消耗，并且在其操作期间获得增加的电荷泵电流。

    Substrate bias generating circuit
    7.
    发明授权
    Substrate bias generating circuit 失效
    基板偏压发生电路

    公开(公告)号：US4455628A

    公开(公告)日：1984-06-19

    申请号：US439215

    申请日：1982-11-04

    申请人： Hideyuki Ozaki ,  Kazuyasu Fujishima ,  Kazuhiro Shimotori

    发明人： Hideyuki Ozaki ,  Kazuyasu Fujishima ,  Kazuhiro Shimotori

    IPC分类号： G11C11/417 ,  G05F3/20 ,  G11C5/14 ,  G11C11/34 ,  G11C11/4074 ,  G11C11/408 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10 ,  H03K19/094 ,  G11C7/00

    CPC分类号： G11C5/146 ,  G05F3/205 ,  G11C11/4074

    摘要： The disclosure described a substrate bias generating circuit in which an internal RAS (Row Address Strobe) signal and an internal CAS (Column Address Strobe) signal, both of which are synchronized with an external RAS signal and external CAS supplied from outside in addition to self-oscillator, activate circuits comprising capacitors and rectifying elements respectively so as to reduce wattage dissipation thereof during holding time of RAM and be obtained increased charge pump current during operation thereof.

    摘要翻译： 本公开描述了一种衬底偏置产生电路，其中内部＆上行＆行（行地址选通）信号和内部CAS（列地址选通）信号，两者都与外部＆上行＆R信号和从外部提供的外部＆upbar＆C同步 除了自振荡器，分别激活包括电容器和整流元件的电路，以便在RAM的保持时间期间降低功率消耗，并且在其操作期间获得增加的电荷泵电流。

    Semiconductor memory device
    8.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US4575825A

    公开(公告)日：1986-03-11

    申请号：US568139

    申请日：1984-01-04

    申请人： Hideyuki Ozaki ,  Kazuhiro Shimotori ,  Hideshi Miyatake

    发明人： Hideyuki Ozaki ,  Kazuhiro Shimotori ,  Hideshi Miyatake

    IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C11/40

    CPC分类号： G11C7/1045 ,  G11C7/22

    摘要： Disclosed is a semiconductor memory device which is one of three types of semiconductor memory devices, one operable only in page mode, one operable only in nibble and one operable selectively in page mode or nibble mode, being obtained from a partially unconnected semiconductor memory device through alternations in a portions in wiring. The semiconductor memory device includes first and second internal column address strobe signal generator. The second internal column address strobe signal generator has at the first stage thereof a NAND circuit one of inputs to which determines the type of the semiconductor memory device depending on which of three kinds of signals is selected as the input. Selection of such an input is effected by an aluminum wiring process using a mask. Such selection of the input causes variation in the input response characteristics of the output of the second internal column address strobe signal generator, thus providing a desired response appropriate for the selected mode or modes.

    摘要翻译： 公开了一种半导体存储器件，其是三种类型的半导体存储器件之一，一种只能以页模式操作，一种仅可半字节操作，一种可操作地以页模式或半字节模式操作，可从部分未连接的半导体存储器件通过 布线部分的交替。 半导体存储器件包括第一和第二内部列地址选通信号发生器。 第二内部列地址选通信号发生器在其第一级具有根据三种信号中的哪一种被选择作为输入的一个输入端的NAND电路，其确定半导体存储器件的类型。 这种输入的选择通过使用掩模的铝布线处理来实现。 输入的这种选择导致第二内部列地址选通信号发生器的输出的输入响应特性的变化，从而提供适合所选择的模式或方式的期望响应。