公开(公告)号：US20060028858A1

公开(公告)日：2006-02-09

申请号：US11240351

申请日：2005-10-03

申请人： Bryan Atwood ,  Takao Watanabe ,  Takeshi Sakata

发明人： Bryan Atwood ,  Takao Watanabe ,  Takeshi Sakata

IPC分类号： G11C11/24

CPC分类号： G11C7/1039 ,  G11C7/1042 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C11/405 ,  G11C11/4093 ,  G11C2207/2281 ,  G11C2207/229 ,  H01L27/10885 ,  H01L27/10888

摘要： A high capacity, fast access dynamic random access memory is provided. Furthermore, a pipelined write method can be realized at each array block by affixing a latch between the sense amplifier and write data line for each column. In this manner, a data write phase can occur simultaneously with the pre-read phase of the following address. Using this method, the effective access speed to the array block can be increased, yielding a fast access cache memory.

摘要翻译： 提供了高容量，快速访问的动态随机存取存储器。 此外，通过在每个列的读出放大器和写入数据线之间附加锁存器，可以在每个阵列块实现流水线写入方法。 以这种方式，数据写入阶段可以与以下地址的预读取阶段同时发生。 使用这种方法，可以增加对阵列块的有效访问速度，从而产生快速访问高速缓冲存储器。

公开(公告)号：US20050029551A1

公开(公告)日：2005-02-10

申请号：US10774586

申请日：2004-02-10

申请人： Bryan Atwood ,  Takao Watanabe ,  Takeshi Sakata

发明人： Bryan Atwood ,  Takao Watanabe ,  Takeshi Sakata

IPC分类号： H01L27/108 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C11/405 ,  G11C11/4093 ,  H01L21/8242 ,  H01L27/10

CPC分类号： G11C7/1039 ,  G11C7/1042 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C11/405 ,  G11C11/4093 ,  G11C2207/2281 ,  G11C2207/229 ,  H01L27/10885 ,  H01L27/10888

摘要： A high capacity, fast access dynamic random access memory is provided. Furthermore, a pipelined write method can be realized at each array block by affixing a latch between the sense amplifier and write data line for each column. In this manner, a data write phase can occur simultaneously with the pre-read phase of the following address. Using this method, the effective access speed to the array block can be increased, yielding a fast access cache memory.

公开(公告)号：US06958507B2

公开(公告)日：2005-10-25

申请号：US10774586

申请日：2004-02-10

申请人： Bryan Atwood ,  Takao Watanabe ,  Takeshi Sakata

发明人： Bryan Atwood ,  Takao Watanabe ,  Takeshi Sakata

IPC分类号： H01L27/108 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C11/405 ,  G11C11/4093 ,  H01L21/8242 ,  H01L27/10

CPC分类号： G11C7/1039 ,  G11C7/1042 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C11/405 ,  G11C11/4093 ,  G11C2207/2281 ,  G11C2207/229 ,  H01L27/10885 ,  H01L27/10888

摘要： A high capacity, fast access dynamic random access memory is provided. Furthermore, a pipelined write method can be realized at each array block by affixing a latch between the sense amplifier and write data line for each column. In this manner, a data write phase can occur simultaneously with the pre-read phase of the following address. Using this method, the effective access speed to the array block can be increased, yielding a fast access cache memory.

摘要翻译： 提供了高容量，快速访问的动态随机存取存储器。 此外，通过在每个列的读出放大器和写入数据线之间附加锁存器，可以在每个阵列块实现流水线写入方法。 以这种方式，数据写入阶段可以与以下地址的预读取阶段同时发生。 使用这种方法，可以增加对阵列块的有效访问速度，从而产生快速访问高速缓冲存储器。

公开(公告)号：US07636808B2

公开(公告)日：2009-12-22

申请号：US10790880

申请日：2004-03-03

申请人： Satoru Akiyama ,  Takeshi Sakata ,  Takao Watanabe

发明人： Satoru Akiyama ,  Takeshi Sakata ,  Takao Watanabe

IPC分类号： G06F12/08 ,  G11C8/00

CPC分类号： G06F12/0804 ,  G06F12/0864 ,  G06F12/0893 ,  G06F2212/2024

摘要： A semiconductor device employs a SESO memory or a phase change memory which has a smaller memory cell area than SRAM. The semiconductor device has a plurality of memory banks each composed of the SESO or phase change memories, and a cache memory which has a number of ways equal to the ratio of a write speed (m) to a read speed (n). The semiconductor device controls the cache memory such that a write back operation is not repeated on the same memory bank.

摘要翻译： 半导体器件采用具有比SRAM更小的存储单元面积的SESO存储器或相变存储器。 半导体器件具有各自由SESO或相变存储器构成的多个存储体，以及高速缓冲存储器，其具有等于写入速度（m）与读取速度（n）的比例的多个方式。 半导体器件控制高速缓冲存储器，使得在相同的存储体上不重复写回操作。

公开(公告)号：US08138442B2

公开(公告)日：2012-03-20

申请号：US12093836

申请日：2005-11-16

申请人： Tatsushi Sato ,  Yoshihito Imai ,  Teiji Takahashi ,  Takeshi Sakata ,  Tomoko Sendai ,  Yoichiro Nishimoto ,  Shigeru Matsuno ,  Takeyuki Maegawa ,  Takaaki Iwata

发明人： Tatsushi Sato ,  Yoshihito Imai ,  Teiji Takahashi ,  Takeshi Sakata ,  Tomoko Sendai ,  Yoichiro Nishimoto ,  Shigeru Matsuno ,  Takeyuki Maegawa ,  Takaaki Iwata

IPC分类号： B23H7/02 ,  H01L21/301 ,  H01L21/306 ,  B23H9/00

CPC分类号： B23H7/02 ,  B23H9/00

摘要： Provided are a wire electric discharge machining method for poorly conductive materials, such as solar cell silicon, and a semiconductor wafer manufacturing method and a solar battery cell manufacturing method based on the wire electric discharge machining method. Electrical discharge machining of a high volume resistivity, hard and brittle materials, having a volume resistivity that is equal to or higher than 0.5 Ω·cm and equal to or lower than 5 Ω·cm is performed by applying a pulse voltage having a pulse width that is equal to or higher than 1 μsec and equal to or lower than 4 μsec and having a peak current at the time of machining a wire electrode that is equal to or higher than 10A and equal to or lower than 50A to a wire electrode and generating a discharge pulse between the wire electrode and a subject to be machined.

摘要翻译： 本发明提供一种导电材料的导电放电加工方法，例如太阳能电池硅，半导体晶片的制造方法以及基于该放电加工方法的太阳能电池单元的制造方法。 具有体积电阻率等于或大于0.5且OHgr·cm且等于或小于5Ω的体积电阻率，硬脆材料的放电加工是通过施加具有 脉冲宽度等于或高于1微秒并且等于或低于4微秒，并且在将线电极加工时的峰值电流等于或高于10A并等于或低于50A的线 并且在线电极和待加工对象之间产生放电脉冲。

公开(公告)号：US07619911B2

公开(公告)日：2009-11-17

申请号：US10579911

申请日：2003-11-21

申请人： Satoru Hanzawa ,  Junji Shigeta ,  Shinichiro Kimura ,  Takeshi Sakata ,  Riichiro Takemura ,  Kazuhiko Kajigaya

发明人： Satoru Hanzawa ,  Junji Shigeta ,  Shinichiro Kimura ,  Takeshi Sakata ,  Riichiro Takemura ,  Kazuhiko Kajigaya

IPC分类号： G11C15/00

CPC分类号： G11C15/04 ,  G11C15/043

摘要： In a memory array structured of memory cells using a storage circuit STC and a comparator CP, either one electrode of a source electrode or a drain electrode of a transistor, whose gate electrode is connected to a search line, of a plurality of transistors structuring the comparator CP is connected to a match line HMLr precharged to a high voltage. Further, a match detector MDr is arranged on a match line LMLr precharged to a low voltage to discriminate a comparison signal voltage generated at the match line according to the comparison result of data. According to such memory array structure and operation, comparison operation can be performed at low power and at high speed while influence of search-line noise is avoided in a match line pair. Therefore, a low power content addressable memory which allows search operation at high speed can be realized.

摘要翻译： 在使用存储电路STC和比较器CP的存储器单元构成的存储器阵列中，将栅电极连接到搜索线的晶体管的源电极或漏电极的一个电极，构成 比较器CP连接到预充电到高电压的匹配线HMLr。 此外，匹配检测器MDr布置在预充电到低电压的匹配线LMLr上，以根据数据的比较结果来识别在匹配线处产生的比较信号电压。 根据这种存储器阵列结构和操作，可以在低功率和高速度下执行比较操作，同时在匹配线对中避免搜索线噪声的影响。 因此，可以实现允许高速搜索操作的低功率内容可寻址存储器。

公开(公告)号：US07505296B2

公开(公告)日：2009-03-17

申请号：US11877310

申请日：2007-10-23

申请人： Satoru Hanzawa ,  Takeshi Sakata ,  Kazuhiko Kajigaya

发明人： Satoru Hanzawa ,  Takeshi Sakata ,  Kazuhiko Kajigaya

IPC分类号： G11C15/00

CPC分类号： G11C15/04 ,  G11C15/043

摘要： The range-specified IP addresses are effectively stored to reduce the number of necessary entries thereby the memory capacity of TCAM is improved. The representative means of the present invention is that: the storage information (entry) and the input information (comparison information or search key) are the common block code such that any bit must be the logical value ‘1’; Match-lines are hierarchically structured and memory cells are arranged at the intersecting points of a plurality of sub-match lines and a plurality of search lines; Further the sub-match lines are connected to main-match lines through the sub-match detectors, respectively and main-match detectors are arranged on the main-match lines.

摘要翻译： 有效存储范围指定的IP地址，以减少必要条目的数量，从而提高TCAM的存储容量。 本发明的代表性手段是：存储信息（条目）和输入信息（比较信息或搜索关键字）是公共块码，使得任何位必须是逻辑值“1”; 匹配线是分层结构的，并且存储器单元被布置在多个子匹配线和多条搜索线的交叉点处; 此外，子匹配线分别通过子匹配检测器连接到主匹配线，并且主匹配检测器被布置在主匹配线上。

公开(公告)号：US07397878B2

公开(公告)日：2008-07-08

申请号：US10377720

申请日：2003-03-04

申请人： Yuichi Okuda ,  Takeshi Sakata ,  Takashi Sato

发明人： Yuichi Okuda ,  Takeshi Sakata ,  Takashi Sato

IPC分类号： H04L7/02

CPC分类号： H04L25/14 ,  H04L7/033 ,  H04L25/4908

摘要： The present invention provides a data communication method and a data communication device capable of performing high-speed data communication by using a parallel link and higher-speed data communication by reducing a timing skew. A data communication method includes: a step of encoding data of N bits (N being 2 or larger) to transmission data of M bits (M being 3 or larger) on a transmission side; a step of generating a transmission signal in which transition takes place in at least one level of any of the transmission data synchronously with a transmission clock and transmitting the transmission signal to a transmission line on the transmission side; a step of recognizing transition in the signal of M bits received via the transmission line and detecting the reception data of M bits synchronized with the transmission clock on a reception side; and a step of decoding the reception data of M bits to the data of N bits.

公开(公告)号：US20080089137A1

公开(公告)日：2008-04-17

申请号：US11873254

申请日：2007-10-16

申请人： Satoru HANZAWA ,  Takeshi Sakata

发明人： Satoru HANZAWA ,  Takeshi Sakata

IPC分类号： G11C7/10

CPC分类号： G11C29/787 ,  G11C7/14 ,  G11C11/1673 ,  G11C11/1693

摘要： A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first dummy cells MCH for storing “1” or “0”, arranged at points of intersection between the word lines WR0 to WR7 and a first dummy data line, and a plurality of second dummy cells MCL for storing “0”, arranged at points of intersection between the word lines WR0 to WR7 and a second dummy data line DD1.

摘要翻译： 虚拟单元包括：多个第一存储单元MC，用于存储多个字线WR0至WR7与多个第一数据线D 0至D 7之间的交点处的“1”或“0” 多个用于存储“1”或“0”的第一虚拟单元MCH，布置在字线WR0至WR7和第一虚拟数据线之间的交点处，以及多个第二虚拟单元MCL，用于存储“0” “，布置在字线WR0至WR7之间的交点处和第二伪数据线DD 1之间。

公开(公告)号：US20080061298A1

公开(公告)日：2008-03-13

申请号：US11931369

申请日：2007-10-31

申请人： Kazuo YANO ,  Tomoyuki Ishii ,  Takashi Hashimoto ,  Koichi Seki ,  Masakazu Aoki ,  Takeshi Sakata ,  Yoshinobu Nakagome ,  Kan Takeuchi

发明人： Kazuo YANO ,  Tomoyuki Ishii ,  Takashi Hashimoto ,  Koichi Seki ,  Masakazu Aoki ,  Takeshi Sakata ,  Yoshinobu Nakagome ,  Kan Takeuchi

IPC分类号： H01L29/04 ,  H01L29/78

CPC分类号： B82Y10/00 ,  G11C11/22 ,  G11C11/404 ,  G11C16/02 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/28 ,  G11C2216/06 ,  G11C2216/08 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11551 ,  H01L27/1203 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/7613 ,  H01L29/785 ,  H01L29/7888

摘要： A semiconductor memory device includes a plurality of memory cells, each including, a source region formed of a semiconductor material, a drain region formed of the semiconductor material, and a first region formed of the semiconductor material and located between the source region and the drain region. First and second insulator films sandwich the first region and a first gate electrode is connected to the first region through the first insulator film. In this arrangement, the first region is adapted to accumulate charges corresponding to stored information.

摘要翻译： 半导体存储器件包括多个存储器单元，每个存储单元包括由半导体材料形成的源极区域，由半导体材料形成的漏极区域和由半导体材料形成并位于源极区域和漏极之间的第一区域 地区。 第一和第二绝缘膜夹着第一区域，第一栅电极通过第一绝缘膜连接到第一区域。 在这种布置中，第一区域适于累积对应于存储的信息的费用。