公开(公告)号：US20050255642A1

公开(公告)日：2005-11-17

申请号：US10842454

申请日：2004-05-11

申请人： Chi-Wen Liu ,  Jung-Chih Tsao

发明人： Chi-Wen Liu ,  Jung-Chih Tsao

IPC分类号： H01L21/28 ,  H01L21/302 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/336 ,  H01L21/338 ,  H01L21/461 ,  H01L21/4763 ,  H01L21/768 ,  H01L29/49

CPC分类号： H01L21/76885 ,  H01L21/28079 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/7684 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/66583

摘要： A method of fabricating an inlaid structure. A sacrificial layer having a trench opening over a substrate is provided. A metal layer is deposited over the sacrificial layer filling the trench openings. A first CMP is performed to remove excess metal layer above the sacrificial layer to form an interconnect structure. The sacrificial layer is removed to expose the interconnect structure. A first dielectric layer is deposited over the substrate covering the interconnect structure. A second CMP is performed on the first dielectric layer to planarize the first dielectric layer.

摘要翻译： 一种制造镶嵌结构的方法。 提供了在衬底上具有沟槽开口的牺牲层。 在填充沟槽开口的牺牲层上沉积金属层。 执行第一CMP以去除牺牲层上方的多余金属层以形成互连结构。 去除牺牲层以露出互连结构。 在覆盖互连结构的衬底上沉积第一介电层。 在第一电介质层上执行第二CMP以使第一电介质层平坦化。

公开(公告)号：US07071100B2

公开(公告)日：2006-07-04

申请号：US10788912

申请日：2004-02-27

申请人： Kei-Wei Chen ,  Jung-Chih Tsao ,  Chi-Wen Liu ,  Jchung-Chang Chen ,  Shih-Tzung Chang ,  Shih-Ho Lin ,  Yu-Ku Lin ,  Ying-Lang Wang

发明人： Kei-Wei Chen ,  Jung-Chih Tsao ,  Chi-Wen Liu ,  Jchung-Chang Chen ,  Shih-Tzung Chang ,  Shih-Ho Lin ,  Yu-Ku Lin ,  Ying-Lang Wang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76844 ,  H01L21/76807 ,  H01L21/76862 ,  H01L21/76865

摘要： A method for forming a copper dual damascene with improved copper migration resistance and improved electrical resistivity including providing a semiconductor wafer including upper and lower dielectric insulating layers separated by a middle etch stop layer; forming a dual damascene opening extending through a thickness of the upper and lower dielectric insulating layers wherein an upper trench line portion extends through the upper dielectric insulating layer thickness and partially through the middle etch stop layer; blanket depositing a barrier layer including at least one of a refractory metal and refractory metal nitride to line the dual damascene opening; carrying out a remote plasma etch treatment of the dual damascene opening to remove a bottom portion of the barrier layer to reveal an underlying conductive area; and, filling the dual damascene opening with copper to provide a substantially planar surface.

摘要翻译： 一种用于形成具有改善的铜迁移阻力和改善的电阻率的铜双镶嵌的方法，包括提供包括由中间蚀刻停止层分隔的上和下介电绝缘层的半导体晶片; 形成延伸通过上下介电绝缘层的厚度的双镶嵌开口，其中上沟槽线部分延伸穿过上介电绝缘层的厚度并部分地穿过中蚀刻停止层; 毯子沉积包括难熔金属和难熔金属氮化物中的至少一种的阻挡层，以便排列双镶嵌开口; 对双镶嵌开口执行远程等离子体蚀刻处理以去除阻挡层的底部以露出下面的导电区域; 并且用铜填充双镶嵌开口以提供基本平坦的表面。

公开(公告)号：US20050191855A1

公开(公告)日：2005-09-01

申请号：US10788912

申请日：2004-02-27

申请人： Kei-Wei Chen ,  Jung-Chih Tsao ,  Chi-Wen Liu ,  Jchung-Chang Chen ,  Shih-Tzung Chang ,  Shih-Ho Lin ,  Yu-Ku Lin ,  Ying-Lang Wang

发明人： Kei-Wei Chen ,  Jung-Chih Tsao ,  Chi-Wen Liu ,  Jchung-Chang Chen ,  Shih-Tzung Chang ,  Shih-Ho Lin ,  Yu-Ku Lin ,  Ying-Lang Wang

IPC分类号： H01L21/44 ,  H01L21/768

CPC分类号： H01L21/76844 ,  H01L21/76807 ,  H01L21/76862 ,  H01L21/76865

摘要： A method for forming a copper dual damascene with improved copper migration resistance and improved electrical resistivity including providing a semiconductor wafer including upper and lower dielectric insulating layers separated by a middle etch stop layer; forming a dual damascene opening extending through a thickness of the upper and lower dielectric insulating layers wherein an upper trench line portion extends through the upper dielectric insulating layer thickness and partially through the middle etch stop layer; blanket depositing a barrier layer including at least one of a refractory metal and refractory metal nitride to line the dual damascene opening; carrying out a remote plasma etch treatment of the dual damascene opening to remove a bottom portion of the barrier layer to reveal an underlying conductive area; and, filling the dual damascene opening with copper to provide a substantially planar surface.

摘要翻译： 一种用于形成具有改善的铜迁移阻力和改善的电阻率的铜双镶嵌的方法，包括提供包括由中间蚀刻停止层分隔的上和下介电绝缘层的半导体晶片; 形成延伸通过上下介电绝缘层的厚度的双镶嵌开口，其中上沟槽线部分延伸穿过上介电绝缘层的厚度并部分地穿过中蚀刻停止层; 毯子沉积包括难熔金属和难熔金属氮化物中的至少一种的阻挡层，以便排列双镶嵌开口; 对双镶嵌开口执行远程等离子体蚀刻处理以去除阻挡层的底部以露出下面的导电区域; 并且用铜填充双镶嵌开口以提供基本平坦的表面。

公开(公告)号：US20050056544A1

公开(公告)日：2005-03-17

申请号：US10664347

申请日：2003-09-16

申请人： Chi-Wen Liu ,  Jung-Chih Tsao ,  Ke-Wei Chen ,  Ying-Lang Wang

发明人： Chi-Wen Liu ,  Jung-Chih Tsao ,  Ke-Wei Chen ,  Ying-Lang Wang

IPC分类号： C25D5/02 ,  C25D5/48 ,  B23H7/26

CPC分类号： C25D5/48 ,  C25D5/028 ,  Y10S204/07

摘要： A dual contact ring for contacting a patterned surface of a wafer and electrochemical plating of a metal on the patterned central region of the wafer and removing the metal from the outer, edge region of the wafer. The dual contact ring has an outer voltage ring in contact with the outer, edge region of the wafer and an inner voltage ring in contact with the inner, central region of the wafer. The outer voltage ring is connected to a positive voltage source and the inner voltage ring is connected to a negative voltage source. The inner voltage ring applies a negative voltage to the wafer to facilitate the plating of metal onto the patterned region of the wafer. A positive voltage is applied to the wafer through the outer voltage ring to remove the plated metal from the outer, edge region of the substrate.

摘要翻译： 用于接触晶片的图案化表面的双接触环和在晶片的图案化中心区域上的金属的电化学电镀，并从晶片的外边缘区域移除金属。 双接触环具有与晶片的外部边缘区域接触的外部电压环和与晶片的内部中心区域接触的内部电压环。 外部电压环连接到正电压源，内部电压环连接到负电压源。 内部电压环向晶片施加负电压以便于将金属电镀到晶片的图案化区域上。 通过外部电压环将正电压施加到晶片，以从衬底的外部边缘区域去除镀覆的金属。

公开(公告)号：US08247322B2

公开(公告)日：2012-08-21

申请号：US11680981

申请日：2007-03-01

申请人： Shih-Chieh Chang ,  Ying-Lang Wang ,  Kei-Wei Chen ,  Jung-Chih Tsao ,  Yu-Sheng Wang

发明人： Shih-Chieh Chang ,  Ying-Lang Wang ,  Kei-Wei Chen ,  Jung-Chih Tsao ,  Yu-Sheng Wang

IPC分类号： H01L21/44

CPC分类号： H01L21/76831 ,  H01L21/7684

摘要： A method for forming a semiconductor structure includes forming a dielectric layer over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed over the first non-conductive barrier layer and within the opening. At least a portion of the second non-conductive barrier layer is removed, thereby at least partially exposing a top surface of the first non-conductive barrier layer and a bottom surface of the opening, with the second non-conductive barrier layer remaining on sidewalls of the opening. A seed layer and conductive layer is then formed and a single polishing operation removes the seed layer and conductive layer.

摘要翻译： 形成半导体结构的方法包括在衬底上形成电介质层。 在电介质层上形成第一非导电阻挡层。 通过第一非导电阻挡层和介电层内形成至少一个开口。 在第一非导电阻挡层上并在开口内形成第二非导电阻挡层。 去除第二非导电阻挡层的至少一部分，从而至少部分地暴露第一非导电阻挡层的顶表面和开口的底表面，而第二非导电阻挡层保留在侧壁上 的开幕。 然后形成种子层和导电层，并且单次抛光操作去除种子层和导电层。

公开(公告)号：US08552529B2

公开(公告)日：2013-10-08

申请号：US13488958

申请日：2012-06-05

申请人： Jung-Chih Tsao ,  Yu-Sheng Wang ,  Kei-Wei Chen ,  Ying-Lang Wang

发明人： Jung-Chih Tsao ,  Yu-Sheng Wang ,  Kei-Wei Chen ,  Ying-Lang Wang

IPC分类号： H01L21/02

CPC分类号： H01L27/0805 ,  H01L28/60 ,  H01L28/75

摘要： A semiconductor device is disclosed. The device includes a substrate; a first metal layer overlying the substrate; a dielectric layer overlying the first metal layer; and a second metal layer overlying the dielectric layer, wherein the first metal layer comprises: a first body-centered cubic lattice metal layer; a first underlayer, underlying the first body-centered cubic lattice metal layer, wherein the first underlayer is metal of body-centered cubic lattice and includes titanium (Ti), tungsten (W), molybdenum (Mo) or niobium (Nb); and a first interface of body-centered cubic lattice between the first body-centered cubic lattice metal layer and the first underlayer.

摘要翻译： 公开了一种半导体器件。 该装置包括基板; 覆盖衬底的第一金属层; 覆盖在第一金属层上的电介质层; 以及覆盖所述电介质层的第二金属层，其中所述第一金属层包括：第一体心立方晶格金属层; 第一底层，位于第一体心立方晶格金属层下面，其中第一底层是体心立方晶格的金属，包括钛（Ti），钨（W），钼（Mo）或铌（Nb）; 以及在第一体心立方晶格金属层和第一底层之间的体心立方晶格的第一界面。

公开(公告)号：US20080211106A1

公开(公告)日：2008-09-04

申请号：US11680981

申请日：2007-03-01

申请人： Shih-Chieh Chang ,  Ying-Lang Wang ,  Kei-Wei Chen ,  Jung-Chih Tsao ,  Yu-Sheng Wang

发明人： Shih-Chieh Chang ,  Ying-Lang Wang ,  Kei-Wei Chen ,  Jung-Chih Tsao ,  Yu-Sheng Wang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76831 ,  H01L21/7684

摘要： A method for forming a semiconductor structure includes forming a dielectric layer over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed over the first non-conductive barrier layer and within the opening. At least a portion of the second non-conductive barrier layer is removed, thereby at least partially exposing a top surface of the first non-conductive barrier layer and a bottom surface of the opening, with the second non-conductive barrier layer remaining on sidewalls of the opening. A seed layer and conductive layer is then formed and a single polishing operation removes the seed layer and conductive layer.

摘要翻译： 形成半导体结构的方法包括在衬底上形成电介质层。 在电介质层上形成第一非导电阻挡层。 通过第一非导电阻挡层和介电层内形成至少一个开口。 在第一非导电阻挡层上并在开口内形成第二非导电阻挡层。 去除第二非导电阻挡层的至少一部分，从而至少部分地暴露第一非导电阻挡层的顶表面和开口的底表面，而第二非导电阻挡层保留在侧壁上 的开幕。 然后形成种子层和导电层，并且单次抛光操作去除种子层和导电层。

公开(公告)号：US07368379B2

公开(公告)日：2008-05-06

申请号：US11197009

申请日：2005-08-04

申请人： Jung-Chih Tsao ,  Kei-Wei Chen ,  Yu-Ku Lin ,  Chyi S Chern

发明人： Jung-Chih Tsao ,  Kei-Wei Chen ,  Yu-Ku Lin ,  Chyi S Chern

IPC分类号： H01L21/3205

CPC分类号： C25D5/10 ,  C25D5/18 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76847 ,  H01L21/76877

摘要： An interconnect structure for a semiconductor device and its method of manufacture is provided. The interconnect structure includes a multi-layer structure having one or more stress-relief layers. In an embodiment, stress-relief layers are positioned between layers of electroplated copper or other conductive material. The stress-relief layer counteracts stress induced by the conductive material and helps prevent or reduce a pull-back void. For an interconnect structure using electroplated copper, the stress-relief layer may be formed by temporarily reducing the electroplating current, thereby causing a thin film of copper having a larger grain size to be formed between other layers of copper. The larger grain size typically exhibits more of a compressive stress than copper with a smaller grain size. The stress relief layer may also be formed of other materials, such as SIP-Cu, Ta, SiC, or the like.

摘要翻译： 提供了半导体器件的互连结构及其制造方法。 互连结构包括具有一个或多个应力消除层的多层结构。 在一个实施例中，应力消除层位于电镀铜或其它导电材料的层之间。 应力消除层抵消由导电材料引起的应力，并有助于防止或减少拉回空隙。 对于使用电镀铜的互连结构，可以通过暂时减少电镀电流来形成应力消除层，从而在其它铜层之间形成具有较大晶粒尺寸的铜的薄膜。 较大的晶粒尺寸通常表现出比具有较小晶粒尺寸的铜更多的压缩应力。 应力消除层也可以由其它材料形成，例如SIP-Cu，Ta，SiC等。

公开(公告)号：US20070152342A1

公开(公告)日：2007-07-05

申请号：US11323484

申请日：2005-12-30

申请人： Jung-Chih Tsao ,  Kei-Wei Chen ,  Ying-Jing Lu ,  Yu-Sheng Wang ,  Yu-Ku Lin

发明人： Jung-Chih Tsao ,  Kei-Wei Chen ,  Ying-Jing Lu ,  Yu-Sheng Wang ,  Yu-Ku Lin

IPC分类号： H01L23/52

CPC分类号： H01L21/76844 ,  H01L21/76805 ,  H01L21/76846 ,  H01L21/76865 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Via structure and process flow for interconnection in a semiconductor product. A bottom metal layer is provided to represent a connection layer in the semiconductor product. An isolation layer on the bottom metal layer comprises a via hole exposing a portion of the bottom metal layer. The via hole comprises a sidewall and a bottom. A first barrier metal layer is disposed on the sidewall of the via hole, but not on the bottom of the via hole. A metal under-layer is formed on the bottom of the via hole and on the first barrier metal layer. A second barrier metal layer is formed on the metal under-layer. A metal fill layer fills the via hole. A lattice mismatch between the metal under-layer and the second barrier metal layer is less than about 5%.

摘要翻译： 通过半导体产品互连的结构和工艺流程。 提供底部金属层以表示半导体产品中的连接层。 底部金属层上的隔离层包括露出底部金属层的一部分的通孔。 通孔包括侧壁和底部。 第一阻挡金属层设置在通孔的侧壁上，但不设置在通孔的底部。 在通孔的底部和第一阻挡金属层上形成金属底层。 在金属底层上形成第二阻挡金属层。 金属填充层填充通孔。 金属底层和第二阻挡金属层之间的晶格失配小于约5％。

公开(公告)号：US20070126120A1

公开(公告)日：2007-06-07

申请号：US11294789

申请日：2005-12-06

申请人： Jung-Chih Tsao ,  Kei-Wei Chen ,  Yu-Ku Lin

发明人： Jung-Chih Tsao ,  Kei-Wei Chen ,  Yu-Ku Lin

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L23/5226 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/76844 ,  H01L21/76846 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： Semiconductor devices and methods for fabricating the same. An exemplary device includes a substrate, a dielectric layer, a protection layer, and a conformal barrier layer. The dielectric layer overlies the substrate and comprises an opening. The opening comprises a lower portion and a wider upper portion, exposing parts of the substrate. The bottoms of the upper portion act as shoulders of the opening. The protection layer overlies at least one shoulder of the opening. The conformal barrier layer is disposed in the opening and overlies the protection layer and the dielectric layer, wherein etching resistance of the protection layer against inert-gas plasma is higher than that of the barrier layer.

摘要翻译： 半导体器件及其制造方法。 示例性器件包括衬底，电介质层，保护层和共形阻挡层。 电介质层覆盖在衬底上并且包括开口。 开口包括下部和较宽的上部，暴露基底的部分。 上部的底部作为开口的肩部。 保护层覆盖开口的至少一个肩部。 共形阻挡层设置在开口中并覆盖保护层和电介质层，其中保护层对惰性气体等离子体的耐蚀性高于阻挡层的抗蚀性。