公开(公告)号：US06943395B2

公开(公告)日：2005-09-13

申请号：US10805696

申请日：2004-03-22

申请人： Hyung-Rok Oh ,  Beak-Hyung Cho ,  Du-Eung Kim ,  Woo-Yeong Cho

发明人： Hyung-Rok Oh ,  Beak-Hyung Cho ,  Du-Eung Kim ,  Woo-Yeong Cho

IPC分类号： G11C13/00 ,  G11B7/24 ,  G11C11/56 ,  G11C16/02 ,  H01L27/10 ,  H01L27/105 ,  H01L27/24 ,  H01L29/76 ,  H01L45/00 ,  H01L47/00

CPC分类号： G11C13/0004 ,  G11C11/5678 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/122 ,  H01L45/144

摘要： A phase random access memory including a plurality of access transistors, each access transistor including a drain region, and a phase-changeable film shared by the plurality of access transistors. The phase-changeable film is connected to a bitline through a first electrode and connected to each respective drain region through at least one of a plurality of second electrodes.

公开(公告)号：US07391644B2

公开(公告)日：2008-06-24

申请号：US11605212

申请日：2006-11-29

申请人： Woo-Yeong Cho ,  Byung-Gil Choi ,  Du-Eung Kim ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Yu-Hwan Ro

发明人： Woo-Yeong Cho ,  Byung-Gil Choi ,  Du-Eung Kim ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Yu-Hwan Ro

IPC分类号： G11C11/00

CPC分类号： G11C8/10 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/72

摘要： Disclosed is a phase-changeable memory device and a related method of reading data. The memory device is comprised of memory cells, a high voltage circuit, a precharging circuit, a bias circuit, and a sense amplifier. Each memory cell includes a phase-changeable material and a diode connected to a bitline. The high voltage circuit provides a high voltage from a power source. The precharging circuit raises the bitline up to the high voltage after charging the bitline up to the power source voltage. The bias circuit supplies a read current to the bitline by means of the high voltage. The sense amplifier compares a voltage of the bitline with a reference voltage by means of the high voltage, and reads data from the memory cell. The memory device is able to reduce the burden on the high voltage circuit during the precharging operation, thus assuring a sufficient sensing margin during the sensing operation.

摘要翻译： 公开了一种可变相存储器件和读取数据的相关方法。 存储器件包括存储器单元，高压电路，预充电电路，偏置电路和读出放大器。 每个存储单元包括相位可变材料和连接到位线的二极管。 高压电路从电源提供高电压。 预充电电路将位线充电至电源电压后，将位线升高至高电压。 偏置电路通过高电压向位线提供读取电流。 读出放大器通过高电压将位线的电压与参考电压进行比较，并从存储单元读取数据。 存储器件能够减少在预充电操作期间对高压电路的负担，从而在感测操作期间确保足够的感测余量。

公开(公告)号：US20090225590A1

公开(公告)日：2009-09-10

申请号：US12453420

申请日：2009-05-11

申请人： Hyung-rok Oh ,  Woo-Yeong Cho ,  Beak-hyung Cho

发明人： Hyung-rok Oh ,  Woo-Yeong Cho ,  Beak-hyung Cho

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C8/10 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0054

摘要： Provided is a phase change random access (PRAM) memory. The PRAM may include a memory cell array having a plurality of phase change memory cells, and a data read circuit including a compensation unit and a sense amplifier, the compensation unit configured to provide a sensing node with a compensation current to compensate for a decrease in a level of the sensing node caused by a current flowing through one of the plurality of phase change memory cells, and the sense amplifier configured to compare a level of the sensing node with a reference level and output a result of the comparison.

公开(公告)号：US07245543B2

公开(公告)日：2007-07-17

申请号：US11249858

申请日：2005-10-13

申请人： Hyung-Rok Oh ,  Woo-Yeong Cho ,  Choong-Keun Kwak

发明人： Hyung-Rok Oh ,  Woo-Yeong Cho ,  Choong-Keun Kwak

IPC分类号： G11C7/00

CPC分类号： G11C13/004 ,  G11C7/06 ,  G11C7/12 ,  G11C13/0004 ,  G11C13/0026 ,  G11C2013/0054 ,  G11C2207/005

摘要： A data read circuit and method for use in a semiconductor memory device that has a memory cell array are provided. The circuit includes a selector for selecting a unit cell within the memory cell array in response to an address signal; a clamping unit for supplying a clamp voltage having a level for a read operation to a bit line of the selected unit cell in response to a clamp control signal; a precharge unit for precharging a sensing node to a voltage having a power source level in response to a control signal of a first state in a precharge mode, and compensating through the sensing node for a reduced quantity of current at the bit line in response to a control signal of a second state in a data sensing mode; and a sense amplifier unit for comparing a level of the sensing node with a reference level, and for sensing data stored in the selected unit cell.

摘要翻译： 提供了一种用于具有存储单元阵列的半导体存储器件中的数据读取电路和方法。 该电路包括：选择器，用于响应于地址信号选择存储单元阵列内的单位单元; 夹紧单元，用于响应于钳位控制信号，将具有用于读取操作的电平的钳位电压提供给所选择的单位单元的位线; 预充电单元，用于响应于在预充电模式中的第一状态的控制信号，将感测节点预充电到具有电源电平的电压，并且响应于位线在位线处减少的电流量补偿 在数据感测模式中的第二状态的控制信号; 以及感测放大器单元，用于将感测节点的电平与参考电平进行比较，并且用于感测存储在所选择的单位单元中的数据。

公开(公告)号：US07245526B2

公开(公告)日：2007-07-17

申请号：US11319266

申请日：2005-12-29

申请人： Hyung-Rok Oh ,  Woo-Yeong Cho ,  Hye-Jin Kim

发明人： Hyung-Rok Oh ,  Woo-Yeong Cho ,  Hye-Jin Kim

IPC分类号： G11C11/00

CPC分类号： G11C13/004 ,  G11C7/12 ,  G11C13/0004 ,  G11C13/0026 ,  G11C2213/79

摘要： A semiconductor memory device includes a plurality of phase change memory cells connected to the same bitline and different respective word lines. A read operation is performed on one of the memory cells by selecting the bitline and a corresponding wordline. While the read operation is performed, leakage current produced by non-selected memory cells is detected by a leakage detecting circuit and compensated by a leakage current supply circuit.

摘要翻译： 半导体存储器件包括连接到同一位线和不同相应字线的多个相变存储器单元。 通过选择位线和相应的字线，对存储器单元之一执行读取操作。 在执行读取操作的同时，由漏电检测电路检测由未选择的存储单元产生的漏电流，并由泄漏电流供给电路进行补偿。

公开(公告)号：US20050030814A1

公开(公告)日：2005-02-10

申请号：US10943300

申请日：2004-09-17

申请人： Hyung-Rok Oh ,  Woo-Yeong Cho ,  Choong-Keun Kwak

发明人： Hyung-Rok Oh ,  Woo-Yeong Cho ,  Choong-Keun Kwak

IPC分类号： G11C13/00 ,  G11C7/06 ,  G11C7/12 ,  G11C13/02 ,  G11C16/02 ,  G11C16/26 ,  H01L27/105 ,  H01L45/00 ,  G11C7/00

CPC分类号： G11C13/004 ,  G11C7/06 ,  G11C7/12 ,  G11C13/0004 ,  G11C13/0026 ,  G11C2013/0054 ,  G11C2207/005

摘要： A data read circuit and method for use in a semiconductor memory device that has a memory cell array are provided. The circuit includes a selector for selecting a unit cell within the memory cell array in response to an address signal; a clamping unit for supplying a clamp voltage having a level for a read operation to a bit line of the selected unit cell in response to a clamp control signal; a precharge unit for precharging a sensing node to a voltage having a power source level in response to a control signal of a first state in a precharge mode, and compensating through the sensing node for a reduced quantity of current at the bit line in response to a control signal of a second state in a data sensing mode; and a sense amplifier unit for comparing a level of the sensing node with a reference level, and for sensing data stored in the selected unit cell.

摘要翻译： 提供了一种用于具有存储单元阵列的半导体存储器件中的数据读取电路和方法。 该电路包括：选择器，用于响应于地址信号选择存储单元阵列内的单位单元; 夹紧单元，用于响应于钳位控制信号，将具有用于读取操作的电平的钳位电压提供给所选择的单位单元的位线; 预充电单元，用于响应于在预充电模式中的第一状态的控制信号，将感测节点预充电到具有电源电平的电压，并且响应于位线在位线处减少的电流量补偿 在数据感测模式中的第二状态的控制信号; 以及感测放大器单元，用于将感测节点的电平与参考电平进行比较，并且用于感测存储在所选择的单位单元中的数据。

公开(公告)号：US07838862B2

公开(公告)日：2010-11-23

申请号：US11177115

申请日：2005-07-08

申请人： Hyung-Rok Oh ,  Beak-Hyung Cho ,  Du-Eung Kim ,  Woo-Yeong Cho

发明人： Hyung-Rok Oh ,  Beak-Hyung Cho ,  Du-Eung Kim ,  Woo-Yeong Cho

IPC分类号： H01L47/00

CPC分类号： G11C13/0004 ,  G11C11/5678 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/122 ,  H01L45/144

摘要： A phase random access memory including a plurality of access transistors, each access transistor including a drain region and a phase-changeable film shared by the plurality of access transistors. The phase-changeable film is connected to a bitline through a first electrode and connected to each respective drain region through at least one of a plurality of second electrodes.

摘要翻译： 一种包括多个存取晶体管的相位随机存取存储器，每个存取晶体管包括漏区和由多个存取晶体管共享的相变膜。 相变膜通过第一电极连接到位线，并通过多个第二电极中的至少一个连接到每个相应的漏极区域。

公开(公告)号：US07463509B2

公开(公告)日：2008-12-09

申请号：US11260602

申请日：2005-10-27

申请人： Hye-Jin Kim ,  Woo-Yeong Cho ,  Hyung-Rok Oh

发明人： Hye-Jin Kim ,  Woo-Yeong Cho ,  Hyung-Rok Oh

IPC分类号： G11C11/00

CPC分类号： H03L7/0812 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/16 ,  G11C11/5607 ,  G11C2211/5615 ,  H01L27/228 ,  H03L7/0891

摘要： A magnetic random access memory (RAM) with a multi-bit cell array structure includes an access transistor formed on a substrate, first through third resistance-variable elements, and first through third current supplying lines. The first through third resistance-variable elements are disposed between a bit line and the access transistor, and electrically connected to each other. The first through third current supplying lines are stacked alternately with the first through third resistance-variable elements. The first through third resistance-variable elements have equal resistances.

摘要翻译： 具有多比特单元阵列结构的磁随机存取存储器（RAM）包括形成在基片上的存取晶体管，第一至第三电阻可变元件以及第一至第三电流线。 第一至第三电阻可变元件设置在位线和存取晶体管之间，并且彼此电连接。 第一至第三电流供应线与第一至第三电阻可变元件交替堆叠。 第一至第三电阻可变元件具有相等的电阻。

公开(公告)号：US20070133271A1

公开(公告)日：2007-06-14

申请号：US11605212

申请日：2006-11-29

申请人： Woo-Yeong Cho ,  Byung-Gil Choi ,  Du-Eung Kim ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Yu-Hwan Ro

发明人： Woo-Yeong Cho ,  Byung-Gil Choi ,  Du-Eung Kim ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Yu-Hwan Ro

IPC分类号： G11C11/00

CPC分类号： G11C8/10 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/72

摘要： Disclosed is a phase-changeable memory device and a related method of reading data. The memory device is comprised of memory cells, a high voltage circuit, a precharging circuit, a bias circuit, and a sense amplifier. Each memory cell includes a phase-changeable material and a diode connected to a bitline. The high voltage circuit provides a high voltage from a power source. The precharging circuit raises the bitline up to the high voltage after charging the bitline up to the power source voltage. The bias circuit supplies a read current to the bitline by means of the high voltage. The sense amplifier compares a voltage of the bitline with a reference voltage by means of the high voltage, and reads data from the memory cell. The memory device is able to reduce the burden on the high voltage circuit during the precharging operation, thus assuring a sufficient sensing margin during the sensing operation.

摘要翻译： 公开了一种可变相存储器件和读取数据的相关方法。 存储器件包括存储器单元，高压电路，预充电电路，偏置电路和读出放大器。 每个存储单元包括相位可变材料和连接到位线的二极管。 高压电路从电源提供高电压。 预充电电路将位线充电至电源电压后，将位线升高至高电压。 偏置电路通过高电压向位线提供读取电流。 读出放大器通过高电压将位线的电压与参考电压进行比较，并从存储单元读取数据。 存储器件能够减少在预充电操作期间对高压电路的负担，从而在感测操作期间确保足够的感测余量。

公开(公告)号：US20060034112A1

公开(公告)日：2006-02-16

申请号：US11249858

申请日：2005-10-13

申请人： Hyung-Rok Oh ,  Woo-Yeong Cho ,  Choong-Keun Kwak

发明人： Hyung-Rok Oh ,  Woo-Yeong Cho ,  Choong-Keun Kwak

IPC分类号： G11C11/00

CPC分类号： G11C13/004 ,  G11C7/06 ,  G11C7/12 ,  G11C13/0004 ,  G11C13/0026 ,  G11C2013/0054 ,  G11C2207/005

摘要： A data read circuit and method for use in a semiconductor memory device that has a memory cell array are provided. The circuit includes a selector for selecting a unit cell within the memory cell array in response to an address signal; a clamping unit for supplying a clamp voltage having a level for a read operation to a bit line of the selected unit cell in response to a clamp control signal; a precharge unit for precharging a sensing node to a voltage having a power source level in response to a control signal of a first state in a precharge mode, and compensating through the sensing node for a reduced quantity of current at the bit line in response to a control signal of a second state in a data sensing mode; and a sense amplifier unit for comparing a level of the sensing node with a reference level, and for sensing data stored in the selected unit cell.

摘要翻译： 提供了一种用于具有存储单元阵列的半导体存储器件中的数据读取电路和方法。 该电路包括：选择器，用于响应于地址信号选择存储单元阵列内的单位单元; 夹紧单元，用于响应于钳位控制信号，将具有用于读取操作的电平的钳位电压提供给所选择的单位单元的位线; 预充电单元，用于响应于在预充电模式中的第一状态的控制信号，将感测节点预充电到具有电源电平的电压，并且响应于位线在位线处减少的电流量补偿 在数据感测模式中的第二状态的控制信号; 以及感测放大器单元，用于将感测节点的电平与参考电平进行比较，并且用于感测存储在所选择的单位单元中的数据。