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    Memory cell array biasing method and a semiconductor memory device
    21.
    发明授权
    Memory cell array biasing method and a semiconductor memory device 有权
    存储单元阵列偏置方法和半导体存储器件

    公开(公告)号：US08248842B2

    公开(公告)日：2012-08-21

    申请号：US12732990

    申请日：2010-03-26

    申请人： Beak-Hyung Cho ,  Do-Eung Kim ,  Choong-Keun Kwak ,  Sang-Beom Kang ,  Woo-Yeong Cho ,  Hyung-Rok Oh

    发明人： Beak-Hyung Cho ,  Do-Eung Kim ,  Choong-Keun Kwak ,  Sang-Beom Kang ,  Woo-Yeong Cho ,  Hyung-Rok Oh

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0023 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/72

    摘要： A method of biasing a memory cell array during a data writing operation and a semiconductor memory device, in which the semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line of a plurality of first lines and a second terminal of the memory cell is connected to a corresponding second line of a plurality of second lines; a bias circuit for biasing a selected second line of the second lines to a reference voltage and a non-selected second line to a first voltage; and a local word line address decoder applying the reference voltage or a pumping voltage corresponding to the first voltage to the bias circuit.

    摘要翻译： 一种在数据写入操作期间偏置存储单元阵列的方法和半导体存储器件，其中半导体存储器件包括：存储单元阵列，其包括多个存储单元，其中存储单元的第一端子连接到 多个第一行的对应的第一行和存储单元的第二端连接到多条第二行的对应的第二行; 偏置电路，用于将所选择的第二行的第二行偏置为参考电压和未选择的第二行至第一电压; 以及本地字线地址解码器将对应于第一电压的参考电压或泵浦电压施加到偏置电路。

    Memory cell of a resistive semiconductor memory device, a resistive semiconductor memory device having a three-dimensional stack structure, and related methods
    22.
    发明授权
    Memory cell of a resistive semiconductor memory device, a resistive semiconductor memory device having a three-dimensional stack structure, and related methods 有权
    电阻半导体存储器件的存储单元，具有三维堆叠结构的电阻半导体存储器件及相关方法

    公开(公告)号：US07843715B2

    公开(公告)日：2010-11-30

    申请号：US12015624

    申请日：2008-01-17

    申请人： Joon-Min Park ,  Sang-Beom Kang ,  Hyung-Rok Oh ,  Woo-Yeong Cho

    发明人： Joon-Min Park ,  Sang-Beom Kang ,  Hyung-Rok Oh ,  Woo-Yeong Cho

    IPC分类号： G11C5/02

    CPC分类号： G11C5/02 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0023 ,  G11C2213/71 ,  G11C2213/72

    摘要： A memory cell of a resistive semiconductor memory device, a resistive semiconductor memory device having a three-dimensional stack structure, and related methods are provided. The memory cell of a resistive semiconductor memory device includes a twin cell, wherein the twin cell stores data values representing one bit of data. The twin cell includes a main unit cell connected to a main bit line and a word line, and a sub unit cell connected to a sub bit line and the word line. Also, the main unit cell includes a first variable resistor and a first diode, and the sub unit cell includes a second variable resistor and a second diode.

    摘要翻译： 提供了电阻半导体存储器件的存储单元，具有三维堆叠结构的电阻半导体存储器件及相关方法。 电阻半导体存储器件的存储单元包括双胞胎，其中双胞胎存储表示一位数据的数据值。 双胞胎单元包括连接到主位线和字线的主单元，以及连接到子位线和字线的子单元。 此外，主单元包括第一可变电阻器和第一二极管，并且子单元电池包括第二可变电阻器和第二二极管。

    Resistance semiconductor memory device having three-dimensional stack and word line decoding method thereof
    24.
    发明授权
    Resistance semiconductor memory device having three-dimensional stack and word line decoding method thereof 有权
    具有三维堆叠和字线解码方法的电阻半导体存储器件

    公开(公告)号：US07808811B2

    公开(公告)日：2010-10-05

    申请号：US12020237

    申请日：2008-01-25

    申请人： Joon-Min Park ,  Sang-Beom Kang ,  Hyung-Rok Oh ,  Woo-Yeong Cho

    发明人： Joon-Min Park ,  Sang-Beom Kang ,  Hyung-Rok Oh ,  Woo-Yeong Cho

    IPC分类号： G11C11/00

    CPC分类号： G11C8/08 ,  G11C8/14 ,  G11C11/16 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0028 ,  G11C2213/71 ,  G11C2213/72

    摘要： A resistance semiconductor memory device of a three-dimensional stack structure, and a word line decoding method thereof, are provided. In the resistance semiconductor memory device of a three-dimensional stack structure, in which a plurality of word line layers and a plurality of bit line layers are disposed alternately and perpendicularly, and in which a plurality of memory cell layers are disposed between the word line layers and the bit line layers; the resistance semiconductor memory device includes a plurality of bit lines disposed on each of the bit line layers in a first direction as a length direction; a plurality of sub word lines disposed on each of the word line layers in a second direction as a length direction, intersected to the first direction; a plurality of memory cells disposed on the memory cell layers; and a plurality of main word lines individually disposed on a main word line layer specifically adapted over the bit line layers and the word line layers, in the second direction as a length direction, each one of the plurality of main word lines being shared by a predetermined number of sub word lines. An efficient word line decoding adequate to high integration can be achieved.

    摘要翻译： 提供三维堆栈结构的电阻半导体存储器件及其字线解码方法。 在三维堆叠结构的电阻半导体存储器件中，其中多个字线层和多个位线层交替和垂直地布置，并且其中多个存储单元层设置在字线 层和位线层; 电阻半导体存储器件包括沿着第一方向设置在每个位线层上的多个位线作为长度方向; 在与第一方向相交的长度方向的第二方向上配置在每个字线层上的多个子字线; 设置在所述存储单元层上的多个存储单元; 以及多个主字线分别设置在主字线层上，特别适用于位线层和字线层，在第二方向上作为长度方向，多个主字线中的每一条由 预定数量的子字线。 可以实现足够高集成度的有效的字线解码。

    MEMORY CELL ARRAY BIASING METHOD AND A SEMICONDUCTOR MEMORY DEVICE
    25.
    发明申请
    MEMORY CELL ARRAY BIASING METHOD AND A SEMICONDUCTOR MEMORY DEVICE 有权
    存储单元阵列偏移方法和半导体存储器件

    公开(公告)号：US20100246248A1

    公开(公告)日：2010-09-30

    申请号：US12732990

    申请日：2010-03-26

    申请人： BEAK-HYUNG CHO ,  Do-Eung Kim ,  Choong-Keun Kwak ,  Sang-Beom Kang ,  Woo-Yeong Cho ,  Hyung-Rok Oh

    发明人： BEAK-HYUNG CHO ,  Do-Eung Kim ,  Choong-Keun Kwak ,  Sang-Beom Kang ,  Woo-Yeong Cho ,  Hyung-Rok Oh

    IPC分类号： G11C11/00 ,  G11C8/08

    CPC分类号： G11C13/0023 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/72

    摘要： A method of biasing a memory cell array during a data writing operation and a semiconductor memory device, in which the semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line of a plurality of first lines and a second terminal of the memory cell is connected to a corresponding second line of a plurality of second lines; a bias circuit for biasing a selected second line of the second lines to a reference voltage and a non-selected second line to a first voltage; and a local word line address decoder applying the reference voltage or a pumping voltage corresponding to the first voltage to the bias circuit.

    摘要翻译： 一种在数据写入操作期间偏置存储单元阵列的方法和半导体存储器件，其中半导体存储器件包括：存储单元阵列，其包括多个存储单元，其中存储单元的第一端子连接到 多个第一行的对应的第一行和存储单元的第二端连接到多条第二行的对应的第二行; 偏置电路，用于将所选择的第二行的第二行偏置为参考电压和未选择的第二行至第一电压; 以及本地字线地址解码器将对应于第一电压的参考电压或泵浦电压施加到偏置电路。

    Magneto-resistive RAM having multi-bit cell array structure
    26.
    发明授权
    Magneto-resistive RAM having multi-bit cell array structure 有权
    具有多位单元阵列结构的磁阻RAM

    公开(公告)号：US07463509B2

    公开(公告)日：2008-12-09

    申请号：US11260602

    申请日：2005-10-27

    申请人： Hye-Jin Kim ,  Woo-Yeong Cho ,  Hyung-Rok Oh

    发明人： Hye-Jin Kim ,  Woo-Yeong Cho ,  Hyung-Rok Oh

    IPC分类号： G11C11/00

    CPC分类号： H03L7/0812 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/16 ,  G11C11/5607 ,  G11C2211/5615 ,  H01L27/228 ,  H03L7/0891

    摘要： A magnetic random access memory (RAM) with a multi-bit cell array structure includes an access transistor formed on a substrate, first through third resistance-variable elements, and first through third current supplying lines. The first through third resistance-variable elements are disposed between a bit line and the access transistor, and electrically connected to each other. The first through third current supplying lines are stacked alternately with the first through third resistance-variable elements. The first through third resistance-variable elements have equal resistances.

    摘要翻译： 具有多比特单元阵列结构的磁随机存取存储器（RAM）包括形成在基片上的存取晶体管，第一至第三电阻可变元件以及第一至第三电流线。 第一至第三电阻可变元件设置在位线和存取晶体管之间，并且彼此电连接。 第一至第三电流供应线与第一至第三电阻可变元件交替堆叠。 第一至第三电阻可变元件具有相等的电阻。

    Phase-changeable memory device and read method thereof
    28.
    发明申请
    Phase-changeable memory device and read method thereof 有权
    相变存储器件及其读取方法

    公开(公告)号：US20070133271A1

    公开(公告)日：2007-06-14

    申请号：US11605212

    申请日：2006-11-29

    申请人： Woo-Yeong Cho ,  Byung-Gil Choi ,  Du-Eung Kim ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Yu-Hwan Ro

    发明人： Woo-Yeong Cho ,  Byung-Gil Choi ,  Du-Eung Kim ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Yu-Hwan Ro

    IPC分类号： G11C11/00

    CPC分类号： G11C8/10 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/72

    摘要： Disclosed is a phase-changeable memory device and a related method of reading data. The memory device is comprised of memory cells, a high voltage circuit, a precharging circuit, a bias circuit, and a sense amplifier. Each memory cell includes a phase-changeable material and a diode connected to a bitline. The high voltage circuit provides a high voltage from a power source. The precharging circuit raises the bitline up to the high voltage after charging the bitline up to the power source voltage. The bias circuit supplies a read current to the bitline by means of the high voltage. The sense amplifier compares a voltage of the bitline with a reference voltage by means of the high voltage, and reads data from the memory cell. The memory device is able to reduce the burden on the high voltage circuit during the precharging operation, thus assuring a sufficient sensing margin during the sensing operation.

    摘要翻译： 公开了一种可变相存储器件和读取数据的相关方法。 存储器件包括存储器单元，高压电路，预充电电路，偏置电路和读出放大器。 每个存储单元包括相位可变材料和连接到位线的二极管。 高压电路从电源提供高电压。 预充电电路将位线充电至电源电压后，将位线升高至高电压。 偏置电路通过高电压向位线提供读取电流。 读出放大器通过高电压将位线的电压与参考电压进行比较，并从存储单元读取数据。 存储器件能够减少在预充电操作期间对高压电路的负担，从而在感测操作期间确保足够的感测余量。

    Data read circuit for use in a semiconductor memory and a method therefor
    29.
    发明申请
    Data read circuit for use in a semiconductor memory and a method therefor 有权
    用于半导体存储器的数据读取电路及其方法

    公开(公告)号：US20060034112A1

    公开(公告)日：2006-02-16

    申请号：US11249858

    申请日：2005-10-13

    申请人： Hyung-Rok Oh ,  Woo-Yeong Cho ,  Choong-Keun Kwak

    发明人： Hyung-Rok Oh ,  Woo-Yeong Cho ,  Choong-Keun Kwak

    IPC分类号： G11C11/00

    CPC分类号： G11C13/004 ,  G11C7/06 ,  G11C7/12 ,  G11C13/0004 ,  G11C13/0026 ,  G11C2013/0054 ,  G11C2207/005

    摘要： A data read circuit and method for use in a semiconductor memory device that has a memory cell array are provided. The circuit includes a selector for selecting a unit cell within the memory cell array in response to an address signal; a clamping unit for supplying a clamp voltage having a level for a read operation to a bit line of the selected unit cell in response to a clamp control signal; a precharge unit for precharging a sensing node to a voltage having a power source level in response to a control signal of a first state in a precharge mode, and compensating through the sensing node for a reduced quantity of current at the bit line in response to a control signal of a second state in a data sensing mode; and a sense amplifier unit for comparing a level of the sensing node with a reference level, and for sensing data stored in the selected unit cell.

    摘要翻译： 提供了一种用于具有存储单元阵列的半导体存储器件中的数据读取电路和方法。 该电路包括：选择器，用于响应于地址信号选择存储单元阵列内的单位单元; 夹紧单元，用于响应于钳位控制信号，将具有用于读取操作的电平的钳位电压提供给所选择的单位单元的位线; 预充电单元，用于响应于在预充电模式中的第一状态的控制信号，将感测节点预充电到具有电源电平的电压，并且响应于位线在位线处减少的电流量补偿 在数据感测模式中的第二状态的控制信号; 以及感测放大器单元，用于将感测节点的电平与参考电平进行比较，并且用于感测存储在所选择的单位单元中的数据。