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    Network function virtualization architecture with device isolation
    26.
    发明授权
    Network function virtualization architecture with device isolation 有权

    公开(公告)号：US10445272B2

    公开(公告)日：2019-10-15

    申请号：US16027776

    申请日：2018-07-05

    Applicant: Intel Corporation

    Inventor： Kevin Devey ,  John Browne ,  Chris Macnamara ,  Eoin Walsh ,  Bruce Richardson ,  Andrew Cunningham ,  Niall Power ,  David Hunt ,  Changzheng Wei ,  Eliezer Tamir

    IPC: G06F13/38 ,  G06F1/3203 ,  G06F9/455 ,  G06F9/4401

    Abstract: A network system includes a central processing unit and a peripheral device in electrical communication with the central processing unit. The peripheral device has at least one power input and a data input. The network system also includes an out of band controller in electrical communication with the central processing unit, the peripheral device, and an external management interface. Responsive to an identified threat, the out of band controller is configured to disable the at least one power input and the data input to the peripheral device, where the disablement indicates to the central processing unit that a hot plug event has occurred with respect to the peripheral device. The out of band controller is also configured to enable auxiliary power to the peripheral device such that the out of band controller remains in communication with the peripheral device during remediation of the identified threat.

    NETWORK FUNCTION VIRTUALIZATION ARCHITECTURE WITH DEVICE ISOLATION
    28.
    发明申请
    NETWORK FUNCTION VIRTUALIZATION ARCHITECTURE WITH DEVICE ISOLATION 审中-公开

    公开(公告)号：US20190042506A1

    公开(公告)日：2019-02-07

    申请号：US16027776

    申请日：2018-07-05

    Applicant: Intel Corporation

    Inventor： Kevin Devey ,  John Browne ,  Chris Macnamara ,  Eoin Walsh ,  Bruce Richardson ,  Andrew Cunningham ,  Niall Power ,  David Hunt ,  Changzheng Wei ,  Eliezer Tamir

    IPC: G06F13/38 ,  G06F1/32 ,  G06F9/455

    Abstract: A network system includes a central processing unit and a peripheral device in electrical communication with the central processing unit. The peripheral device has at least one power input and a data input. The network system also includes an out of band controller in electrical communication with the central processing unit, the peripheral device, and an external management interface. Responsive to an identified threat, the out of band controller is configured to disable the at least one power input and the data input to the peripheral device, where the disablement indicates to the central processing unit that a hot plug event has occurred with respect to the peripheral device. The out of band controller is also configured to enable auxiliary power to the peripheral device such that the out of band controller remains in communication with the peripheral device during remediation of the identified threat.

    TECHNOLOGIES FOR DEMOTING CACHE LINES TO SHARED CACHE
    29.
    发明申请
    TECHNOLOGIES FOR DEMOTING CACHE LINES TO SHARED CACHE 审中-公开

    公开(公告)号：US20190042419A1

    公开(公告)日：2019-02-07

    申请号：US16024773

    申请日：2018-06-30

    Applicant: Intel Corporation

    Inventor： Eliezer Tamir ,  Bruce Richardson ,  Niall Power ,  Andrew Cunningham ,  David Hunt ,  Kevin Devey ,  Changzheng Wei

    IPC: G06F12/084 ,  G06F12/1072

    Abstract: Technologies for demoting cache lines to a shared cache include a compute device with at least one processor having multiple cores, a cache memory with a core-local cache and a shared cache, and a cache line demote device. A processor core of a processor of the compute device is configured to retrieve at least a portion of data of a received network packet and move the data into one or more core-local cache lines of the core-local cache. The processor core is further configured to perform a processing operation on the data and transmit a cache line demotion command to the cache line demote device subsequent to having completed the processing operation. The cache line demote device is configured to perform a cache line demotion operation to demote the data from the core-local cache lines to shared cache lines of the shared cache. Other embodiments are described herein.

    TECHNOLOGIES FOR MOVING WORKLOADS BETWEEN HARDWARE QUEUE MANAGERS
    30.
    发明申请
    TECHNOLOGIES FOR MOVING WORKLOADS BETWEEN HARDWARE QUEUE MANAGERS 审中-公开

    公开(公告)号：US20190042305A1

    公开(公告)日：2019-02-07

    申请号：US15912746

    申请日：2018-03-06

    Applicant: Intel Corporation

    Inventor： Niall D. McDonnell ,  Debra Bernstein ,  Patrick Fleming ,  Chris Macnamara ,  Andrew Cunningham ,  Bruce Richardson ,  Brendan N. Ryan

    IPC: G06F9/48 ,  G06F9/50

    Abstract: Technologies for moving workloads between hardware queue managers include a compute device. The compute device includes a set of hardware queue managers. Each hardware queue manager is to manage one or more queues of queue elements and each queue element is indicative of a data set to be operated on by a thread. The compute device also includes circuitry to execute a workload with a first hardware queue manager of the set of hardware queue managers, determine whether a workload migration condition is present, determine whether a second hardware queue manager of the set of hardware queue managers has sufficient capacity to manage a set of queues associated with the workload, move, in response to a determination that the second hardware queue manager does have sufficient capacity, the workload to the second hardware queue manager, and reduce, after the move of the workload to the second hardware queue manager, a power usage of the first hardware queue manager.

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