公开(公告)号：US09268393B2

公开(公告)日：2016-02-23

申请号：US13997295

申请日：2012-11-30

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Krishnakanth Sistla ,  Martin T. Rowland ,  Brian J. Griffith ,  Viktor D. Vogman ,  Joseph R. Doucette ,  Eric J. Dehaemer ,  Vivek Garg ,  Chris Poirier ,  Jeremy J. Shrall ,  Avinash N. Ananthakrishnan ,  Stephen H. Gunther

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/06 ,  G06F9/45

CPC classification number: G06F1/3234 ,  G06F1/06 ,  G06F1/324 ,  G06F8/4432 ,  Y02D10/126

Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a plurality of graphics engines each to independently perform graphics operations; and, a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a power excursion control logic to limit a power consumption level of the processor from being above a defined power limit for more than a duty cycle portion of an operating period. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括多个核心，每个核心各自独立地执行指令，多个图形引擎各自独立地执行图形操作; 以及功率控制单元，其耦合到所述多个核以控制所述处理器的功率消耗，其中所述功率控制单元包括功率偏移控制逻辑，以将所述处理器的功率消耗水平限制在高于限定功率极限以上 工作周期的占空比部分。 描述和要求保护其他实施例。

公开(公告)号：US11237614B2

公开(公告)日：2022-02-01

申请号：US16454378

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Malini K. Bhandaru ,  Eric J. Dehaemer ,  Scott P. Bobholz ,  Raghunandan Makaram ,  Vivek Garg

IPC: G06F1/324 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3296 ,  G06F1/3225

Abstract: In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.

公开(公告)号：US10345884B2

公开(公告)日：2019-07-09

申请号：US15238717

申请日：2016-08-16

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Krishnakanth V. Sistla ,  Martin T. Rowland ,  Chris Poirier ,  Eric J. Dehaemer ,  Avinash N. Ananthakrishnan ,  Jeremy J. Shrall ,  Xiuting C. Man ,  Stephen H. Gunther ,  Krishna K. Rangan ,  Devadatta V. Bodas ,  Don C. Soltis, Jr. ,  Hang T. Nguyen ,  Cyprian W. Woo ,  Thi Dang

IPC: G06F9/00 ,  G06F1/3234 ,  G06F1/20 ,  G06F1/3206 ,  G06F1/28

Abstract: One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor.

公开(公告)号：US10331186B2

公开(公告)日：2019-06-25

申请号：US15401276

申请日：2017-01-09

Applicant: Intel Corporation

Inventor： James S. Ignowski ,  Matthew M. Bace ,  Eric J. Dehaemer ,  Chris Poirier

IPC: G06F1/20 ,  G06F1/26 ,  G06F1/28 ,  G06F9/50 ,  G06F1/324 ,  G06F11/07 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3293 ,  G06F1/3296

Abstract: In an embodiment, a processor comprises: a plurality of cores each to execute instructions; a plurality of thermal sensors, at least one of which is associated with each of the cores; and a power control unit (PCU) coupled to the cores. The PCU includes a thermal control logic to preemptively throttle a first core by a first throttle amount when a temperature of a second core exceeds at least one thermal threshold. Note that this first core may be preemptively throttled independently of a throttling of the second core and may have a temperature of the first core does not exceed any thermal threshold. Other embodiments are described and claimed.

公开(公告)号：US10073779B2

公开(公告)日：2018-09-11

申请号：US13729579

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Herbert H. Hum ,  Brinda Ganesh ,  James R. Vash ,  Ganesh Kumar ,  Leena K. Puthiyedath ,  Scott J. Erlanger ,  Eric J. Dehaemer ,  Adrian C. Moga ,  Michelle M. Sebot ,  Richard L. Carlson ,  David Bubien ,  Eric Delano

IPC: G06F12/00 ,  G06F12/0831 ,  G06F12/0811 ,  G06F12/084

CPC classification number: G06F12/0831 ,  G06F12/0811 ,  G06F12/084

Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.

公开(公告)号：US10037227B2

公开(公告)日：2018-07-31

申请号：US14973009

申请日：2015-12-17

Applicant: INTEL CORPORATION

Inventor： Guy Therien ,  Guy Sotomayor ,  Arijit Biswas ,  Michael D. Powell ,  Eric J. Dehaemer

IPC: G06F9/46 ,  G06F9/48 ,  G06F1/32 ,  G06F9/50 ,  G06F9/4401

CPC classification number: G06F9/4856 ,  G06F1/3287 ,  G06F9/4418 ,  G06F9/461 ,  G06F9/4893 ,  G06F9/5094 ,  Y02D10/24 ,  Y02D10/32 ,  Y02D10/44

Abstract: Work can be migrated between processor cores. For example, a thread causing a heavy load on a first core can be detected. A power control unit can determine to migrate the thread from the first less-efficient core to the second more-efficient core. The power control unit can request that the first core and the second core transition to a low-power state (e.g., a sleep state, a C6 power state, etc.). The first core can transfer its software context to a first core software context storage, halt and quiesce. The second core can halt and quiesce. The software context from the first core software context storage can be transferred to a second core software context storage of the second core. A processing core identifier of the first core can be assigned to the second core. The power control unit can then request the second core to transition to an active state (such as a C0 state).

公开(公告)号：US20160170468A1

公开(公告)日：2016-06-16

申请号：US15048189

申请日：2016-02-19

Applicant: Intel Corporation

Inventor： Malini K. Bhandaru ,  Eric J. Dehaemer ,  Scott P. Bobholz ,  Raghunandan Makaram ,  Vivek Garg

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/3225 ,  G06F1/3234 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.

公开(公告)号：US09235244B2

公开(公告)日：2016-01-12

申请号：US13785259

申请日：2013-03-05

Applicant: Intel Corporation

Inventor： Malini K. Bhandaru ,  Eric J. Dehaemer ,  Scott P. Bobholz ,  Raghunandan Makaram ,  Vivek Garg

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/324 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/3225 ,  G06F1/3234 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，多核处理器包括可独立执行指令的核心，每个指令以独立的电压和频率进行。 处理器可以包括具有用于提供处理器的电源管理特征的可配置性的逻辑的功率控制器。 一种这样的特征使得至少一个核可以基于存在于控制寄存器中的单个功率域指示符的状态在独立的性能状态下操作。 描述和要求保护其他实施例。