公开(公告)号：US09780510B2

公开(公告)日：2017-10-03

申请号：US14764931

申请日：2014-09-26

Applicant: INTEL CORPORATION

Inventor： Dhanya Athreya ,  Gaurav Chawla ,  Kemal Aygun ,  Glen P. Gordon ,  Sarah M. Canny ,  Jeffory L. Smalley ,  Srikant Nekkanty ,  Michael Garcia ,  Joshua D. Heppner

IPC: H01R24/00 ,  H01R33/76 ,  H01L23/32 ,  H01L23/498

CPC classification number: H01R33/7685 ,  H01L23/32 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards socket contact techniques and configurations. In one embodiment, an apparatus may include a socket substrate having a first side and a second side disposed opposite to the first side, an opening formed through the socket substrate, an electrical contact disposed in the opening and configured to route electrical signals between the first side and the second side of the socket substrate, the electrical contact having a cantilever portion that extends beyond the first side, wherein the first side and surfaces of the socket substrate in the opening are plated with a metal. Other embodiments may be described and/or claimed.

公开(公告)号：US20160079150A1

公开(公告)日：2016-03-17

申请号：US14484896

申请日：2014-09-12

Applicant: Intel Corporation

Inventor： Gaurav Chawla ,  Joshua D. Heppner ,  Vijaykumar Krithivasan ,  Michael Garcia ,  Kuang C. Liu ,  Rajasekaran Swaminathan

IPC: H01L23/498 ,  H01L23/36 ,  H01L21/48 ,  B23P15/26

CPC classification number: H05K7/20 ,  H01L23/3675 ,  H01L23/4006 ,  H01L23/433 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed toward techniques and configurations associated with a package load assembly. In one embodiment, a package load assembly may include a frame configured to form a perimeter around a die area of a package substrate having a first surface configured to be coupled with a surface of the package substrate and a second surface disposed opposite to the first surface. The frame may include deformable members disposed on the second surface, which may be configured to be coupled with a base of a heat sink to distribute force applied between the heat sink and the package substrate, via the frame, and may deform under application of the force, which may allow the base of the heat sink to contact a surface of an integrated heat spreader within the die area of the package substrate.

Abstract translation: 本公开的实施例涉及与封装负载组件相关联的技术和配置。 在一个实施例中，包装负载组件可以包括框架，该框架被配置为围绕包装衬底的管芯区域形成周边，该封装衬底具有构造成与封装衬底的表面耦合的第一表面和与第一表面相对设置的第二表面 。 框架可以包括设置在第二表面上的可变形构件，其可以被配置为与散热器的底座相耦合，以经由框架分布施加在散热器和封装衬底之间的力，并且可以在应用 力，其可以允许散热器的底部接触在封装衬底的管芯区域内的集成散热器的表面。

公开(公告)号：US11525970B2

公开(公告)日：2022-12-13

申请号：US17083173

申请日：2020-10-28

Applicant: Intel Corporation

Inventor： Shawna Liff ,  Adel A. Elsherbini ,  Telesphor Kamgaing ,  Sasha N. Oster ,  Gaurav Chawla

IPC: G06F13/14 ,  G02B6/42 ,  H01P5/00 ,  H01Q13/10 ,  H04B1/40 ,  H04B7/00 ,  H04M9/06 ,  G06F13/00

Abstract: Microelectronic package communication is described using radio interfaces connected through wiring. One example includes a system board, an integrated circuit chip, and a package substrate mounted to the system board to carry the integrated circuit chip, the package substrate having conductive connectors to connect the integrated circuit chip to external components. A radio on the package substrate is coupled to the integrated circuit chip to modulate the data onto a carrier and to transmit the modulated data. A radio on the system board receives the transmitted modulated data and demodulates the received data, and a cable interface is coupled to the system board radio to couple the received demodulated data to a cable.

公开(公告)号：US10433421B2

公开(公告)日：2019-10-01

申请号：US13727439

申请日：2012-12-26

Applicant: INTEL CORPORATION

Inventor： Zhichao Zhang ,  Tao Wu ,  Gaurav Chawla ,  Jeffrey Lee

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/34

Abstract: A land grid array (LGA) land pad having reduced capacitance is disclosed. The conductive portion of a land pad that overlaps a parallel ground plane within the substrate is reduced by one or more non-conductive voids though the thickness of the conductive portion of the land pad. The voids may allow the contact area of the land pad, as defined by the perimeter of the land pad, to remain the same while reducing the conductive portion that overlaps the parallel ground plane. Capacitance between the land pad and the parallel ground plane is reduced by an amount proportional to the reduction in overlapping conductive area.

公开(公告)号：US09385457B2

公开(公告)日：2016-07-05

申请号：US14563641

申请日：2014-12-08

Applicant: Intel Corporation

Inventor： Gaurav Chawla ,  Joshua D Heppner ,  Zhichao Zhang ,  David J. Llapitan ,  Vijaykumar Krithivasan

IPC: H01R24/28 ,  H01R12/72 ,  H01R12/79 ,  H01R13/11 ,  H01R12/71 ,  H01L23/34 ,  H01R12/70

CPC classification number: H01R12/722 ,  H01L23/34 ,  H01L2924/0002 ,  H01R12/7005 ,  H01R12/71 ,  H01R12/724 ,  H01R12/79 ,  H01R13/114 ,  H01L2924/00

Abstract: Connectors and methods to couple packages and dies are shown. Selected examples include plugs and receptacles having two or more terraces with contacts provided along the terraces. Examples of connectors and methods include configurations where the connector is usable with a package including a die coupled along a substrate. In selected examples a heat sink is coupled over the die, and a package includes a side access port between the heat sink and the substrate configured to receive the connector, such as one or more of a plug or receptacle through the side access port.

Abstract translation: 显示连接器和耦合封装和管芯的方法。 所选择的实例包括具有两个或更多台阶的插头和插座，其具有沿梯田提供的触点。 连接器和方法的示例包括其中连接器可用于包括沿衬底耦合的裸片的封装的配置。 在所选择的示例中，散热器耦合在管芯上，并且封装包括在散热器和被配置为接收连接器的基板之间的侧入口，例如通过侧面接入端口的一个或多个插头或插座。

公开(公告)号：US09017106B2

公开(公告)日：2015-04-28

申请号：US13826393

申请日：2013-03-14

Applicant: Intel Corporation

Inventor： Joshua D Heppner ,  Gaurav Chawla

IPC: H01R24/86 ,  H01R24/60 ,  H01R43/00 ,  H01R12/72 ,  H01R12/79 ,  H01R107/00

CPC classification number: H01R24/86 ,  H01R12/724 ,  H01R12/727 ,  H01R12/79 ,  H01R24/60 ,  H01R43/00 ,  H01R2107/00 ,  Y10T29/49117

Abstract: This disclosure relates generally to a connector assembly. In various examples, first conductive members are secured with respect to one another and form a first row and second conductive members are secured with respect to one another, a first subset of the second conductive members forming a second row and a second subset of the second conductive members forming a third row, the second and third rows being parallel and stacked with respect to one another and the second and third rows being orthogonal to the first row. Individual ones of the first and second conductive members are arranged to be coupled at a first end to a corresponding one of contacts. Ones of the first conductive members are arranged to be coupled to a corresponding individual one of the second conductive members proximate a second end of each of the first and second conductive members.

Abstract translation: 本公开总体上涉及连接器组件。 在各种示例中，第一导电构件相对于彼此固定并形成第一行，并且第二导电构件相对于彼此固定，第二导电构件的第一子集形成第二行，第二子集的第二导电构件 形成第三排的导电构件，第二和第三排相对于彼此平行和堆叠，第二和第三行与第一行正交。 第一和第二导电构件中的各个被布置成在第一端耦合到对应的一个触点。 第一导电部件的一部分布置成接近靠近第一和第二导电部件的每一个的第二端的相应的单独的一个第二导电部件。

公开(公告)号：US08961193B2

公开(公告)日：2015-02-24

申请号：US13712166

申请日：2012-12-12

Applicant: Intel Corporation

Inventor： Gaurav Chawla ,  Vijaykumar Krithivasan ,  Joshua D Heppner

IPC: H01R24/86

CPC classification number: H01R43/20 ,  H01R24/86 ,  H05K7/1084 ,  Y10T29/4922

Abstract: An apparatus for coupling an integrated circuit to other electronics can include a housing having an exterior and an interior, the exterior having an exterior bottom surface, the interior defined by an interior bottom surface opposite the exterior bottom surface, and at least one sidewall extending away from the interior bottom surface to define an interior shape that is sized to receive the integrated circuit, with the integrated circuit disposed against the interior bottom surface and the at least one sidewall. The example can include a plurality of exterior contacts exposed along the exterior bottom surface in an exterior contact pattern that is generally circular in shape.

Abstract translation: 用于将集成电路耦合到其它电子设备的装置可以包括具有外部和内部的外壳，外部具有外部底部表面，内部由与外部底部表面相对的内部底部表面限定，并且至少一个侧壁延伸远离 从内部底部表面限定尺寸适于接收集成电路的内部形状，其中集成电路抵靠内部底部表面和至少一个侧壁设置。 该示例可以包括沿着外部底部表面暴露的多个外部接触件，外部接触图案通常为圆形形状。

公开(公告)号：US08905794B2

公开(公告)日：2014-12-09

申请号：US13711187

申请日：2012-12-11

Applicant: Intel Corporation

Inventor： Gaurav Chawla ,  Joshua D Heppner ,  Zhichao Zhang ,  David J. Llapitan ,  Vijaykumar Krithivasan

IPC: H01R4/66 ,  H01R12/71

CPC classification number: H01R12/722 ,  H01L23/34 ,  H01L2924/0002 ,  H01R12/7005 ,  H01R12/71 ,  H01R12/724 ,  H01R12/79 ,  H01R13/114 ,  H01L2924/00

Abstract: Connectors and methods to couple packages and dies are shown. Selected examples include plugs and receptacles having two or more terraces with contacts provided along the terraces. Examples of connectors and methods include configurations where the connector is usable with a package including a die coupled along a substrate. In selected examples a heat sink is coupled over the die, and a package includes a side access port between the heat sink and the substrate configured to receive the connector, such as one or more of a plug or receptacle through the side access port.

Abstract translation: 显示连接器和耦合封装和管芯的方法。 所选择的实例包括具有两个或更多台阶的插头和插座，其具有沿梯田提供的触点。 连接器和方法的示例包括其中连接器可用于包括沿衬底耦合的裸片的封装的配置。 在所选择的示例中，散热器耦合在管芯上，并且封装包括在散热器和被配置为接收连接器的基板之间的侧入口，例如通过侧面接入端口的一个或多个插头或插座。