公开(公告)号：US20180166363A1

公开(公告)日：2018-06-14

申请号：US15579116

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Joshua D. Heppner ,  Mitul B. Modi

IPC: H01L23/48 ,  H01L23/552 ,  H01L25/065 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/768 ,  H01L23/48 ,  H01L23/552 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06537 ,  H01L2924/19107

Abstract: Semiconductor packages with electromagnetic interference (EMI) shielding structures and a method of manufacture therefor is disclosed. In some aspects, a shielding structure can serve as an enclosure formed by conductive material or by a mesh of such material that can be used to block electric fields emanating from one or more electronic components enclosed by the shielding structure at a global package level or local and/or compartment package level for semiconductor packages. In one embodiment, wire and/or ribbon bonding can be used to fabricate the shielding structure. For example, one or more wire and/or ribbon bonds can go from a connecting ground pad on one side of the package to a connecting ground pad on the other side of the package. This can be repeated multiple times at a pre-determined pitch necessary to meet the electrical requirements for shielding, e.g. less than or equal to approximately one half the wavelength of radiation generated by the electronic components being shielded.

公开(公告)号：US09795026B2

公开(公告)日：2017-10-17

申请号：US14969514

申请日：2015-12-15

Applicant: Intel Corporation

Inventor： Nayandeep K. Mahanta ,  Joshua D. Heppner ,  Adel A. Elsherbini

IPC: H05K1/02 ,  H05K1/18 ,  H05K1/11

CPC classification number: H05K1/0206 ,  H01L23/34 ,  H05K1/115 ,  H05K1/18 ,  H05K2201/095 ,  H05K2201/09854

Abstract: The electronic package includes a substrate that includes a plurality of dielectric layers and conductive routings between the plurality of dielectric layers; wherein the substrate further includes a plurality of thermal finned vias that electrically connect the conductive routings within the substrate to one another; and an electronic component mounted on the substrate, wherein the finned via transfers heat from the electronic component to the substrate and electrically connects the conductive routings within the substrate to the electronic component.

公开(公告)号：US20170271270A1

公开(公告)日：2017-09-21

申请号：US15074050

申请日：2016-03-18

Applicant: Intel Corporation

Inventor： Rajendra C. Dias ,  Anna M. Prakash ,  Joshua D. Heppner ,  Eric J. Li ,  Nachiket R. Raravikar

IPC: H01L23/552 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31

CPC classification number: H01L23/552 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include a substrate including electrical connection circuitry therein, grounding circuitry on, or at least partially in the substrate, the grounding circuitry at least partially exposed from a surface of the substrate, a die electrically connected to the connection circuitry and the grounding circuitry, the die on the substrate, and a conductive foil or conductive film surrounding the die, the conductive foil or conductive film electrically connected to the grounding circuitry.

公开(公告)号：US20170178990A1

公开(公告)日：2017-06-22

申请号：US14973184

申请日：2015-12-17

Applicant: Intel Corporation

Inventor： Sasha Oster ,  Srikant Nekkanty ,  Joshua D. Heppner ,  Adel A. Elsherbini ,  Yoshihiro Tomita ,  Debendra Mallik ,  Shawna M. Liff ,  Yoko Sekihara

IPC: H01L23/31 ,  H01L23/367 ,  H01L23/66 ,  H01L23/00 ,  H01L21/56 ,  H01L23/48 ,  H01L23/58

Abstract: Devices and methods include an electronic package having a through-mold interconnect are shown herein. Examples of the electronic package include a package assembly. The package assembly including a substrate having a first substrate surface. The first substrate surface including a conductive layer attached to the first substrate surface. The package assembly includes a die communicatively coupled to the conductive layer and a contact block. The contact block including a first contact surface on one end of the contact block, a second contact surface on an opposing side of the contact block, and a contact block wall extended therebetween. The contact block includes a conductive material. The first contact surface is coupled to the package assembly with a joint extended partially up the contact block wall. The electronic package further includes an overmold covering portions of the substrate, conductive layer, and die. The second contact surface of the contact block is exposed through the overmold.

公开(公告)号：US11955434B2

公开(公告)日：2024-04-09

申请号：US17861125

申请日：2022-07-08

Applicant: Intel Corporation

Inventor： Yoshihiro Tomita ,  Eric J. Li ,  Shawna M. Liff ,  Javier A. Falcon ,  Joshua D. Heppner

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/552 ,  H01L25/04 ,  H01L25/065 ,  H01L25/07 ,  H01L25/075 ,  H01L25/11 ,  H01L25/16

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/19 ,  H01L24/48 ,  H01L24/96 ,  H01L25/04 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/16 ,  H01L24/16 ,  H01L25/042 ,  H01L25/071 ,  H01L25/072 ,  H01L25/0753 ,  H01L25/112 ,  H01L25/115 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/81024 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/1304 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/13101 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/1304 ,  H01L2924/00012 ,  H01L2924/1436 ,  H01L2924/00012 ,  H01L2924/1203 ,  H01L2924/00012

Abstract: Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.

公开(公告)号：US20180277458A1

公开(公告)日：2018-09-27

申请号：US15992830

申请日：2018-05-30

Applicant: Intel Corporation

Inventor： Sasha Oster ,  Srikant Nekkanty ,  Joshua D. Heppner ,  Adel A. Elsherbini ,  Yoshihiro Tomita ,  Debendra Mallik ,  Shawna M. Liff ,  Yoko Sekihara

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  H01L21/56 ,  H01L23/367 ,  H01L23/66 ,  H01L23/58

Abstract: Devices and methods include an electronic package having a through-mold interconnect are shown herein. Examples of the electronic package include a package assembly. The package assembly including a substrate having a first substrate surface. The first substrate surface including a conductive layer attached to the first substrate surface. The package assembly includes a die communicatively coupled to the conductive layer and a contact block. The contact block including a first contact surface on one end of the contact block, a second contact surface on an opposing side of the contact block, and a contact block wall extended therebetween. The contact block includes a conductive material. The first contact surface is coupled to the package assembly with a joint extended partially up the contact block wall. The electronic package further includes an overmold covering portions of the substrate, conductive layer, and die. The second contact surface of the contact block is exposed through the overmold.

公开(公告)号：US10070520B2

公开(公告)日：2018-09-04

申请号：US14998263

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Yoshihiro Tomita ,  Joshua D. Heppner ,  Shawna M. Liff ,  Pramod Malatkar

IPC: H05K3/00 ,  H05K1/03 ,  H05K1/11 ,  H05K1/18 ,  H05K3/32 ,  A41D1/00 ,  A43B3/00 ,  A41D13/00

Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing a magnetic particle embedded flexible substrate, a printed flexible substrate for a magnetic tray, or an electro-magnetic carrier for magnetized or ferromagnetic flexible substrates. For instance, in accordance with one embodiment, there are means disclosed for fabricating a flexible substrate having one or more electrical interconnects to couple with leads of an electrical device; integrating magnetic particles or ferromagnetic particles into the flexible substrate; supporting the flexible substrate with a carrier plate during one or more manufacturing processes for the flexible substrate, in which the flexible substrate is held flat against the carrier plate by an attractive magnetic force between the magnetic particles or ferromagnetic particles integrated with the flexible substrate and a complementary magnetic attraction of the carrier plate; and removing the flexible substrate from the carrier plate subsequent to completion of the one or more manufacturing processes for the flexible substrate. Other related embodiments are disclosed.

公开(公告)号：US10056182B2

公开(公告)日：2018-08-21

申请号：US14616508

申请日：2015-02-06

Applicant: Intel Corporation

Inventor： Gregorio R. Murtagian ,  Robert L. Sankman ,  Brent S. Stone ,  Kaladhar Radhakrishnan ,  Joshua D. Heppner

IPC: H01F27/29 ,  H01F5/00 ,  H01F27/02 ,  H01L27/08 ,  H05K7/00 ,  H01F27/28 ,  H01F17/04 ,  H01F27/06

CPC classification number: H01F27/2852 ,  H01F17/045 ,  H01F27/02 ,  H01F27/027 ,  H01F27/06 ,  H01F27/2847 ,  H01F27/292 ,  H01F2027/065 ,  H01F2027/297 ,  H01L2224/16225 ,  H01L2924/181 ,  Y10T29/4902 ,  H01L2924/00012

Abstract: Embodiments of the present disclosure are directed towards an inductor structure having one or more strips of conductive material disposed around a core. The strips may have contacts at a first end and a second end of the strips, and may be disposed around the core with a gap between the contacts. The inductor structure may be mounted on a surface of a substrate, and one or more traces may be formed in the surface of the substrate to electrically couple two or more of the strips of conductive material to one another to form inductive coils. Other embodiments may be described and/or claimed.

公开(公告)号：US09953929B2

公开(公告)日：2018-04-24

申请号：US15074050

申请日：2016-03-18

Applicant: Intel Corporation

Inventor： Rajendra C. Dias ,  Anna M. Prakash ,  Joshua D. Heppner ,  Eric J. Li ,  Nachiket R. Raravikar

IPC: H01L23/552 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L23/552 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include a substrate including electrical connection circuitry therein, grounding circuitry on, or at least partially in the substrate, the grounding circuitry at least partially exposed from a surface of the substrate, a die electrically connected to the connection circuitry and the grounding circuitry, the die on the substrate, and a conductive foil or conductive film surrounding the die, the conductive foil or conductive film electrically connected to the grounding circuitry.

公开(公告)号：US20180096862A1

公开(公告)日：2018-04-05

申请号：US15816681

申请日：2017-11-17

Applicant: Intel Corporation

Inventor： Sasha N. Oster ,  Adel A. Elsherbini ,  Joshua D. Heppner ,  Shawna M. Liff

IPC: H01L21/56 ,  H01L23/31

CPC classification number: H01L23/315 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/42 ,  H01L23/4334 ,  H01L23/467 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2224/81

Abstract: Molded electronics package cavities are formed by placing a sacrificial material in the mold and then decomposing, washing, or etching away this sacrificial material. The electronics package that includes this sacrificial material is then overmolded, with little or no change needed in the overmolding process. Following overmolding, the sacrificial material is removed such as using a thermal, chemical, optical, or other decomposing process. This proposed use of sacrificial material allows for formation of complex 3-D cavities, and reduces or eliminates the need for precise material removal tolerances. Multiple instances of the sacrificial material may be removed simultaneously, replacing a serial drilling process with a parallel material removal manufacturing process.