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公开(公告)号：US11658570B2
公开(公告)日：2023-05-23
申请号：US17009661
申请日：2020-09-01
Applicant: Intel Corporation
Inventor： Harish Krishnamurthy , Sheldon Weng , Nachiket Desai , Suhwan Kim , Fabrice Paillet
CPC classification number: H02M3/157 , G06F1/26 , H02M3/1584 , H03H17/0211
Abstract: A digital control scheme controls an integrator of a PID filter to implement non-linear control of saturating the duty cycle during which the proportional and derivative terms of the PID filter are set to 0 while the integrator and its internal states (previous values or memory) is set to a duty cycle that is the sum of the current nominal duty cycle plus a deltaD. The deltaD is the maximum duty cycle increment that is used to regulate a voltage regulator from ICCmin to ICCmax and is a configuration register that can be set post silicon. An FSM moves from a non-linear all ON state to an open loop duty cycle which maintains the output voltage slightly higher than the required Vref. After a certain period in this open loop, the FSM then ramps down the open loop duty cycle value until the output voltage is close to the Vref.
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公开(公告)号：US20210203228A1
公开(公告)日：2021-07-01
申请号：US16727759
申请日：2019-12-26
Applicant: Intel Corporation
Inventor： Xiaosen Liu , Krishnan Ravichandran , Harish Krishnamurthy , Vivek De
Abstract: A 3-level ripple quantization scheme provides power transistor (MOS) strength-tuning mechanism focused on the transient clamp period. The 3-level ripple quantization scheme solves the digital low dropout's (D-LDO's) tradeoff between silicon area (e.g., decoupling capacitor size), quiescent power consumption (e.g., speed of comparators), wide load range, and optimal output ripple. The 3-level ripple quantization scheme eliminates oscillation risk from either wide dynamic range or parasitic by exploiting asynchronous pulse patterns. As such, ripple magnitude for both fast di/dt loading events and various steady-state scenarios are shrunk effectively, resulting significant efficiency benefits.
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公开(公告)号：US10530254B2
公开(公告)日：2020-01-07
申请号：US15632086
申请日：2017-06-23
Applicant: INTEL CORPORATION
Inventor： Khondker Ahmed , Vivek De , Nachiket Desai , Suhwan Kim , Harish Krishnamurthy , Xiaosen Liu , Turbo Majumder , Krishnan Ravichandran , Christopher Schaef , Vaibhav Vaidya , Sriram Vangal
Abstract: Embodiments described herein concern operating a peak-delivered-power (PDP) controller. Operating a PDP includes calculating the new power output value from the output voltage value and the output current value, determining whether the new power output value is greater than the previous power output value to determine whether the voltage regulator is outputting a maximum power output, based on a determination that the new power output value is greater than the previous power output value, providing an instruction to a duty generator to increase a duty cycle of the voltage regulator, based on a determination that the new power output value is not greater than the previous power output value, providing an instruction to the duty generator to decrease the duty cycle of the voltage regulator, and replacing the previous power output value with the new power output value.
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公开(公告)号：US12047485B2
公开(公告)日：2024-07-23
申请号：US17132365
申请日：2020-12-23
Applicant: Intel Corporation
Inventor： Raghavan Kumar , Xiaosen Liu , Harish Krishnamurthy , Sanu Mathew , Vikram Suresh
CPC classification number: H04L9/003 , G06F1/26 , H04L9/0631 , H04L2209/08
Abstract: Apparatus and method for resisting side-channel attacks on cryptographic engines are described herein. An apparatus embodiment includes a cryptographic block coupled to a non-linear low-dropout voltage regulator (NL-LDO). The NL-LDO includes a scalable power train to provide a variable load current to the cryptographic block, randomization circuitry to generate randomized values for setting a plurality of parameters, and a controller to adjust the variable load current provided to the cryptographic block based on the parameters and the current voltage of the cryptographic block. The controller to cause a decrease in the variable load current when the current voltage is above a high voltage threshold, an increase in the variable load current when the current voltage is below a low voltage threshold; and a maximization of the variable load current when the current voltage is below an undervoltage threshold. The cryptographic block may be implemented with arithmetic transformations.
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25.发明授权公开(公告)号：US11940824B2
公开(公告)日：2024-03-26
申请号：US17100603
申请日：2020-11-20
Applicant: Intel Corporation
Inventor： Xiaosen Liu , Harish Krishnamurthy , Krishnan Ravichandran , Vivek De , Scott Chiu , Claudia Patricia Barrera Gonzalez , Jing Han , Rajasekhara Madhusudan Narayana Bhatla
Abstract: Embodiments of the present disclosure describe methods, apparatuses, and systems for hybrid low dropout regulator (LDO) architecture and realization to provide high power supply rejection ratio (PSRR) and high conversion efficiency (CE), and other benefits. The hybrid LDO may be coupled with dual rails for its analog LDO branch and digital LDO respectively to achieve high PSRR and high CE by utilizing the hybrid architecture with several feedback loops. Other embodiments may be described and claimed.
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Patent Agency Ranking
公开(公告)号：US11444532B2
公开(公告)日：2022-09-13
申请号：US16727759
申请日：2019-12-26
Applicant: Intel Corporation
Inventor： Xiaosen Liu , Krishnan Ravichandran , Harish Krishnamurthy , Vivek De
Abstract: A 3-level ripple quantization scheme provides power transistor (MOS) strength-tuning mechanism focused on the transient clamp period. The 3-level ripple quantization scheme solves the digital low dropout's (D-LDO's) tradeoff between silicon area (e.g., decoupling capacitor size), quiescent power consumption (e.g., speed of comparators), wide load range, and optimal output ripple. The 3-level ripple quantization scheme eliminates oscillation risk from either wide dynamic range or parasitic by exploiting asynchronous pulse patterns. As such, ripple magnitude for both fast di/dt loading events and various steady-state scenarios are shrunk effectively, resulting significant efficiency benefits.
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公开(公告)号：US11429172B2
公开(公告)日：2022-08-30
申请号：US16735563
申请日：2020-01-06
Applicant: Intel Corporation
Inventor： Alexander Uan-Zo-Li , Eugene Gorbatov , Harish Krishnamurthy , Alexander Lyakhov , Patrick Leung , Stephen Gunther , Arik Gihon , Khondker Ahmed , Philip Lehwalder , Sameer Shekhar , Vishram Pandit , Nimrod Angel , Michael Zelikson
Abstract: A power supply architecture combines the benefits of a traditional single stage power delivery, when there are no additional power losses in the integrated VR with low VID and low CPU losses of FIVR (fully integrated voltage regulator) and D-LVR (digital linear voltage regulator). The D-LVR is not in series with the main power flow, but in parallel. By placing the digital-LVR in parallel to a primary VR (e.g., motherboard VR), the CPU VID is lowered and the processor core power consumption is lowered. The power supply architecture reduces the guard band for input power supply level, thereby reducing the overall power consumption because the motherboard VR specifications can be relaxed, saving cost and power. The power supply architecture drastically increases the CPU performance at a small extra cost for the silicon and low complexity of tuning.
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公开(公告)号：US11387198B2
公开(公告)日：2022-07-12
申请号：US16635536
申请日：2017-09-29
Applicant: Intel Corporation
Inventor： Wilfred Gomes , Mark Bohr , Doug Ingerly , Rajesh Kumar , Harish Krishnamurthy , Nachiket Venkappayya Desai
IPC: H01L23/64 , H01L21/48 , H01L21/56 , H01L23/498 , H01L23/00 , H01L25/065 , H01L25/00
Abstract: Techniques and mechanisms for providing an inductor with an integrated circuit (IC) die. In an embodiment, the IC die comprises integrated circuitry and one or more first metallization layers. The IC die is configured to couple to a circuit device including one or more second metallization layers, where such coupling results in the formation of an inductor which is coupled to the integrated circuitry. One or more loop structures of the inductor each span both some or all of the one or more first metallization layers and some or all of the one or more second metallization layers. In another embodiment, the IC die or the circuit device includes a ferromagnetic material to concentrate a magnetic flux which is provided with the inductor.
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公开(公告)号：US20220200784A1
公开(公告)日：2022-06-23
申请号：US17132365
申请日：2020-12-23
Applicant: Intel Corporation
Inventor： Raghavan Kumar , Xiaosen Liu , Harish Krishnamurthy , Sanu Mathew , Vikram Suresh
Abstract: Apparatus and method for resisting side-channel attacks on cryptographic engines are described herein. An apparatus embodiment includes a cryptographic block coupled to a non-linear low-dropout voltage regulator (NL-LDO). The NL-LDO includes a scalable power train to provide a variable load current to the cryptographic block, randomization circuitry to generate randomized values for setting a plurality of parameters, and a controller to adjust the variable load current provided to the cryptographic block based on the parameters and the current voltage of the cryptographic block. The controller to cause a decrease in the variable load current when the current voltage is above a high voltage threshold, an increase in the variable load current when the current voltage is below a low voltage threshold; and a maximization of the variable load current when the current voltage is below an undervoltage threshold. The cryptographic block may be implemented with arithmetic transformations.
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公开(公告)号：US20220065901A1
公开(公告)日：2022-03-03
申请号：US17006715
申请日：2020-08-28
Applicant: Intel Corporation
Inventor： Nachiket Desai , Harish Krishnamurthy , Suhwan Kim , Fabrice Paillet
Abstract: A current sensing topology uses an amplifier with capacitively coupled inputs in feedback to sense the input offset of the amplifier, which can be compensated for during measurement. The amplifier with capacitively coupled inputs in feedback is used to: operate the amplifier in a region where the input common-mode specifications are relaxed, so that the feedback loop gain and/or bandwidth is higher; operate the sensor from the converter input voltage by employing high-PSRR (power supply rejection ratio) regulators to create a local, clean supply voltage, causing less disruption to the power grid in the switch area; sample the difference between the input voltage and the controller supply, and recreate that between the drain voltages of the power and replica switches; and compensate for power delivery network related (PDN-related) changes in the input voltage during current sensing.
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