公开(公告)号：US11966286B2

公开(公告)日：2024-04-23

申请号：US17715771

申请日：2022-04-07

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  Rajat Agarwal ,  Jongwon Lee

IPC: G06F11/10 ,  G11C11/4096

CPC classification number: G06F11/1044 ,  G06F11/1072 ,  G11C11/4096

Abstract: A memory device that performs internal ECC (error checking and correction) can selectively return read data with application of the internal ECC or without application of the internal ECC, in response to different read commands from the memory controller. The memory device can normally apply ECC and return corrected data in response to a normal read command. In response to a retry command, the memory device can return the read data without application of the internal ECC.

公开(公告)号：US11335395B2

公开(公告)日：2022-05-17

申请号：US17062420

申请日：2020-10-02

Applicant: Intel Corporation

Inventor： Christopher E. Cox ,  Kuljit S. Bains ,  Christopher P. Mozak ,  James A. McCall ,  Akshith Vasanth ,  Bill Nale

IPC: G11C11/4072 ,  G11C11/4096 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4074 ,  G11C11/406

Abstract: A memory subsystem triggers entry and exit of a memory device from low power mode with a chip select (CS) signal line. For a system where the command bus has no clock enable (CKE) signal line, the system can trigger low power modes with CS instead of CKE. The low power mode can include a powerdown state. The low power mode can include a self-refresh state. The memory device includes an interface to the command bus, and receives a CS signal combined with command encoding on the command bus to trigger a low power mode state change. The memory device can be configured to monitor the CS signal and selected other command signals while in low power mode. The system can send an ODT trigger while the memory device is in low power mode, even without a dedicated ODT signal line.

公开(公告)号：US11314589B2

公开(公告)日：2022-04-26

申请号：US16875642

申请日：2020-05-15

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  Rajat Agarwal ,  Jongwon Lee

IPC: G06F11/10 ,  G11C11/4096

Abstract: A memory device that performs internal ECC (error checking and correction) can selectively return read data with application of the internal ECC or without application of the internal ECC, in response to different read commands from the memory controller. The memory device can normally apply ECC and return corrected data in response to a normal read command. In response to a retry command, the memory device can return the read data without application of the internal ECC.

公开(公告)号：US11056179B2

公开(公告)日：2021-07-06

申请号：US16737666

申请日：2020-01-08

Applicant: Intel Corporation

Inventor： Chong J. Zhao ,  James A. McCall ,  Shigeki Tomishima ,  George Vergis ,  Kuljit S. Bains

IPC: G11C29/02 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/408 ,  H01L27/108

Abstract: Techniques to couple a high bandwidth memory device on a silicon substrate and a package substrate are disclosed. Examples include selectively activating input/out (I/O) or command and address (CA) contacts on a bottom side of a logic layer for the high bandwidth device based on a mode of operation. The I/O and CA contacts are for accessing one or more memory devices include in the high bandwidth memory device via one or more data channels.

公开(公告)号：US10949296B2

公开(公告)日：2021-03-16

申请号：US15681387

申请日：2017-08-20

Applicant: Intel Corporation

Inventor： John B. Halbert ,  Kuljit S. Bains

IPC: G11C29/00 ,  G06F11/10 ,  G11C29/52 ,  G11C29/42 ,  G11C29/44 ,  G11C11/40 ,  G11C29/04 ,  G11C29/56

Abstract: A memory subsystem enables managing error correction information. A memory device internally performs error detection for a range of memory locations, and increments an internal count for each error detected. The memory device includes ECC logic to generate an error result indicating a difference between the internal count and a baseline number of errors preset for the memory device. The memory device can provide the error result to an associated host of the system to expose only a number of errors accumulated without exposing internal errors from prior to incorporation into a system. The memory device can be made capable to generate internal addresses to execute commands received from the memory controller. The memory device can be made capable to reset the counter after a first pass through the memory area in which errors are counted.

公开(公告)号：US10943640B2

公开(公告)日：2021-03-09

申请号：US16177284

申请日：2018-10-31

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  George Vergis ,  James A. McCall ,  Ge Chang

IPC: G06F12/00 ,  G11C11/4074 ,  G06F3/06 ,  G11C7/10 ,  G11C8/06 ,  G06F13/16 ,  G11C11/408

Abstract: Techniques and mechanisms for providing termination for a plurality of chips of a memory device. In an embodiment, a memory device is an integrated circuit (IC) package which includes a command and address bus and a plurality of memory chips each coupled thereto. Of the plurality of memory chips, only a first memory chip is operable to selectively provide termination to the command and address bus. Of the respective on-die termination control circuits of the plurality of memory chips, only the on-die termination control circuit of the first memory chip is coupled via any termination control signal line to any input/output (I/O) contact of the IC package. In another embodiment, the plurality of memory chips are configured in a series with one another, and wherein the first memory chip is located at an end of the series.

公开(公告)号：US10310547B2

公开(公告)日：2019-06-04

申请号：US15266991

申请日：2016-09-15

Applicant: Intel Corporation

Inventor： George Vergis ,  Kuljit S. Bains ,  Bill Nale

IPC: G06F1/06 ,  G06F13/42 ,  G06F3/06 ,  G06F12/00

Abstract: Techniques to include a mirror of a command/address at a memory device. Techniques to also include interpretation of command/address logic. A memory device located on a dual in-line memory module (DIMM) includes circuitry having logic capable of receiving a command/address signal and mirror a command/address or interpret command/address logic indicated in the command/address signal based on one or more strap pins for the memory device.

公开(公告)号：US10224090B2

公开(公告)日：2019-03-05

申请号：US15611455

申请日：2017-06-01

Applicant: Intel Corporation

Inventor： Kuljit S. Bains

IPC: G11C7/00 ,  G11C11/406

Abstract: A memory device includes a per bank refresh counter applicable to multiple banks in a group. The memory device increments a row address counter only when the per bank refresh counter is reset. The memory device receives a per bank refresh command from an associated memory controller, and performs a per bank refresh in response to receiving the per bank refresh command. The memory device refreshes a row identified by a row address counter for a bank identified by the per bank refresh command. The memory device increments the per bank refresh counter in response to receiving the per bank refresh command, and increments the row address counter when the per bank refresh counter is reset, either by rolling over or by a reset condition.

公开(公告)号：US10176138B2

公开(公告)日：2019-01-08

申请号：US15068128

申请日：2016-03-11

Applicant: INTEL CORPORATION

Inventor： Christopher E. Cox ,  Kuljit S. Bains

IPC: G06F3/00 ,  G06F13/12 ,  G06F13/40 ,  G06F13/38 ,  G06F11/30 ,  G06F11/22 ,  G06F11/34

Abstract: Techniques and mechanisms for configuring an integrated circuit to couple to, and exchange data with, a hardware interface. In an embodiment, the integrated circuit comprises a data channel including a plurality of bits, configuration logic, and a plurality of contacts including a first contact group and a second contact group. In response to a signal indicating connectivity of the integrated circuit to the interface, a mode of the configuration logic is selected to couple the plurality of bits to one of the first contact group and the second contact group.

公开(公告)号：US10109340B2

公开(公告)日：2018-10-23

申请号：US15639725

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  John B. Halbert ,  Nadav Bonen ,  Tomer Levy

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/408

Abstract: Memory subsystem refresh management enables commands to access one or more identified banks across different bank groups with a single command. Instead of sending commands identifying a bank or banks in separate bank groups by each bank group individually, the command can cause the memory device to access banks in different bank groups. The command can be a refresh command. The command can be a precharge command.