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    Technologies for efficient LZ77-based data decompression
    22.
    发明授权
    Technologies for efficient LZ77-based data decompression 有权
    技术用于高效的基于LZ77的数据解压缩

    公开(公告)号：US09524169B2

    公开(公告)日：2016-12-20

    申请号：US14494766

    申请日：2014-09-24

    Applicant: Intel Corporation

    Inventor： Vinodh Gopal ,  Sean M. Gulley ,  James D. Guilford

    IPC: G06F9/38 ,  G06F12/02 ,  G06F12/08 ,  H03M7/30

    CPC classification number: H03M7/3086 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/065 ,  G06F3/0673 ,  G06F9/3818 ,  G06F9/3863 ,  G06F12/023 ,  G06F12/0875 ,  G06F2212/1044 ,  G06F2212/452 ,  H03M7/3091 ,  H03M7/6005 ,  H03M7/6017

    Abstract: Technologies for data decompression include a computing device that reads a symbol tag byte from an input stream. The computing device determines whether the symbol can be decoded using a fast-path routine, and if not, executes a slow-path routine to decompress the symbol. The slow-path routine may include data-dependent branch instructions that may be unpredictable using branch prediction hardware. For the fast-path routine, the computing device determines a next symbol increment value, a literal increment value, a data length, and an offset based on the tag byte, without executing an unpredictable branch instruction. The computing device sets a source pointer to either literal data or reference data as a function of the tag byte, without executing an unpredictable branch instruction. The computing device may set the source pointer using a conditional move instruction. The computing device copies the data and processes remaining symbols. Other embodiments are described and claimed.

    Abstract translation: 用于数据解压缩的技术包括从输入流读取符号标记字节的计算设备。 计算设备确定是否可以使用快速路径例程来解码符号，如果不是，则执行慢路径例程来解压缩符号。 慢路径例程可以包括使用分支预测硬件可能不可预测的依赖于数据的分支指令。 对于快速路径例程，计算设备基于标签字节确定下一个符号递增值，文字增量值，数据长度和偏移量，而不执行不可预测的分支指令。 计算设备将源指针设置为文字数据或引用数据作为标记字节的函数，而不执行不可预测的分支指令。 计算设备可以使用条件移动指令来设置源指针。 计算设备复制数据并处理剩余符号。 描述和要求保护其他实施例。

    Generating multiple secure hashes from a single data buffer
    23.
    发明授权
    Generating multiple secure hashes from a single data buffer 有权
    从单个数据缓冲区生成多个安全散列

    公开(公告)号：US09425953B2

    公开(公告)日：2016-08-23

    申请号：US14050326

    申请日：2013-10-09

    Applicant: Intel Corporation

    Inventor： Sean M. Gulley ,  Vinodh Gopal ,  Wajdi K. Feghali ,  James D. Guilford ,  Gilbert M. Wolrich ,  Kirk S. Yap

    IPC: H04L9/06

    CPC classification number: H04L9/0643 ,  G06F9/30007 ,  G06F21/72 ,  H04L9/3242 ,  H04L2209/12 ,  H04L2209/125 ,  H04L2209/20

    Abstract: One embodiment provides an apparatus. The apparatus includes a single instruction multiple data (SIMD) hash module configured to apportion at least a first portion of a message of length L to a number (S) of segments, the message including a plurality of sequences of data elements, each sequence including S data elements, a respective data element in each sequence apportioned to a respective segment, each segment including a number N of blocks of data elements and to hash the S segments in parallel, resulting in S segment digests, the S hash digests based, at least in part, on an initial value and to store the S hash digests; a padding module configured to pad a remainder, the remainder corresponding to a second portion of the message, the second portion related to the length L of the message, the number of segments and a block size; and a non-SIMD hash module configured to hash the padded remainder, resulting in an additional hash digest and to store the additional hash digest.

    Abstract translation: 一个实施例提供了一种装置。 该装置包括单个指令多数据（SIMD）散列模块，其被配置为将长度为L的消息的至少第一部分分配给数量（S）个段，该消息包括多个数据元素序列，每个序列包括 S个数据元素，分配给相应段的每个序列中的相应数据元素，每个段包括N个数据元素块，并且并行地对S个段进行散列，导致S段摘要，基于S个散列摘要 至少部分地在初始值上存储S哈希摘要; 填充模块，被配置为填补余数，剩余部分对应于消息的第二部分，与消息的长度L相关的第二部分，段的数量和块大小; 以及非SIMD散列模块，被配置为对填充的余数进行散列，产生附加的散列摘要并存储附加散列摘要。

    INSTRUCTIONS AND LOGIC TO PROVIDE SIMD SM4 CRYPTOGRAPHIC BLOCK CIPHER FUNCTIONALITY
    24.
    发明申请
    INSTRUCTIONS AND LOGIC TO PROVIDE SIMD SM4 CRYPTOGRAPHIC BLOCK CIPHER FUNCTIONALITY 有权

    公开(公告)号：US20220353070A1

    公开(公告)日：2022-11-03

    申请号：US17718237

    申请日：2022-04-11

    Applicant: Intel Corporation

    Inventor： Sean M. Gulley ,  Gilbert M. Wolrich ,  Vinodh Gopal ,  Kirk S. Yap ,  Wajdi K. Feghali

    IPC: H04L9/08 ,  H04L9/06 ,  G06F21/72 ,  G06F9/30 ,  G09C1/00 ,  G06F9/38

    Abstract: Instructions and logic provide for a Single Instruction Multiple Data (SIMD) SM4 round slice operation. Embodiments of an instruction specify a first and a second source data operand set, and substitution function indicators, e.g. in an immediate operand. Embodiments of a processor may include encryption units, responsive to the first instruction, to: perform a slice of SM4-round exchanges on a portion of the first source data operand set with a corresponding keys from the second source data operand set in response to a substitution function indicator that indicates a first substitution function, perform a slice of SM4 key generations using another portion of the first source data operand set with corresponding constants from the second source data operand set in response to a substitution function indicator that indicates a second substitution function, and store a set of result elements of the first instruction in a SIMD destination register.

    Instructions and logic to provide SIMD SM3 cryptographic hashing functionality
    25.
    发明授权
    Instructions and logic to provide SIMD SM3 cryptographic hashing functionality 有权

    公开(公告)号：US10592245B2

    公开(公告)日：2020-03-17

    申请号：US15600200

    申请日：2017-05-19

    Applicant: Intel Corporation

    Inventor： Gilbert M. Wolrich ,  Vinodh Gopal ,  Sean M. Gulley ,  Kirk S. Yap ,  Wajdi K. Feghali

    IPC: G06F9/30 ,  G06F21/72

    Abstract: Instructions and logic provide SIMD SM3 cryptographic hashing functionality. Some embodiments include a processor comprising: a decoder to decode instructions for a SIMD SM3 message expansion, specifying first and second source data operand sets, and an expansion extent. Processor execution units, responsive to the instruction, perform a number of SM3 message expansions, from the first and second source data operand sets, determined by the specified expansion extent and store the result into a SIMD destination register. Some embodiments also execute instructions for a SIMD SM3 hash round-slice portion of the hashing algorithm, from an intermediate hash value input, a source data set, and a round constant set. Processor execution units perform a set of SM3 hashing round iterations upon the source data set, applying the intermediate hash value input and the round constant set, and store a new hash value result in a SIMD destination register.

    Instructions and logic to provide SIMD SM4 cryptographic block cipher functionality
    28.
    发明授权
    Instructions and logic to provide SIMD SM4 cryptographic block cipher functionality 有权

    公开(公告)号：US10158484B2

    公开(公告)日：2018-12-18

    申请号：US15289819

    申请日：2016-10-10

    Applicant: Intel Corporation

    Inventor： Sean M. Gulley ,  Gilbert M. Wolrich ,  Vinodh Gopal ,  Kirk S. Yap ,  Wajdi K. Feghali

    IPC: H04L9/08 ,  H04L9/06 ,  G06F21/72 ,  G09C1/00 ,  G06F9/30 ,  G06F9/38

    Abstract: Instructions and logic provide for a Single Instruction Multiple Data (SIMD) SM4 round slice operation. Embodiments of an instruction specify a first and a second source data operand set, and substitution function indicators, e.g. in an immediate operand. Embodiments of a processor may include encryption units, responsive to the first instruction, to: perform a slice of SM4-round exchanges on a portion of the first source data operand set with a corresponding keys from the second source data operand set in response to a substitution function indicator that indicates a first substitution function, perform a slice of SM4 key generations using another portion of the first source data operand set with corresponding constants from the second source data operand set in response to a substitution function indicator that indicates a second substitution function, and store a set of result elements of the first instruction in a SIMD destination register.

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