公开(公告)号：US20160378472A1

公开(公告)日：2016-12-29

申请号：US14750940

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： Jayesh Iyer ,  Jamison D. Collins ,  Sebastian Winkel ,  Howard H. Chen

IPC: G06F9/30

CPC classification number: G06F9/30029 ,  G06F9/30054 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/3013

Abstract: A processor includes a front end to receive an instruction. The processor also includes a core to execute the instruction. The core includes logic to execute a base function of the instruction to yield a result, generate a predicate value of a comparison of the result based upon a predication setting in the instruction, and set the predicate value in a register. The processor also includes a retirement unit to retire the instruction.

Abstract translation: 处理器包括用于接收指令的前端。 处理器还包括执行指令的核心。 核心包括执行指令的基本功能以产生结果的逻辑，基于指令中的预测设置产生结果的比较的谓词值，并将谓词值设置在寄存器中。 该处理器还包括一个退休单位退休指导。

公开(公告)号：US11934809B2

公开(公告)日：2024-03-19

申请号：US17053531

申请日：2019-11-06

Applicant: Intel Corporation

Inventor： Junyong Ding ,  Mohammad Haghighat ,  Qi Zhang ,  Sebastian Winkel ,  Tianyou Li

IPC: G06F8/41

CPC classification number: G06F8/41

Abstract: Systems, apparatuses and methods may provide for developer stage technology that embeds binary code into an application binary file, wherein the binary code corresponds to vector functions and non-vector functions in statically typed source code, and generates intermediate representation (IR) data, wherein the intermediate representation data corresponds to the vector functions in the statically typed source code. Additionally, the developer stage technology embeds the IR data in the application binary file. Moreover, deployment stage technology may generate a first compilation output based on the application binary file and detect a capability change in an execution environment associated with the first compilation output. The deployment stage technology may also generate, in response to the detected capability change, a second compilation output based on the first compilation output.

公开(公告)号：US10540178B2

公开(公告)日：2020-01-21

申请号：US15265587

申请日：2016-09-14

Applicant: Intel Corporation

Inventor： Vineeth Mekkat ,  Youfeng Wu ,  Sebastian Winkel ,  Oleg Margulis

IPC: G06F12/0875 ,  G06F9/30 ,  G06F9/38 ,  G06F9/32

Abstract: A processor for redundant stores includes a front end including circuitry to decode instructions from an instruction stream, a data cache unit including circuitry to cache data for the processor, a binary translator, and a memory execution unit. The binary translator includes circuitry to identify a first region of the instruction stream including a redundant store, mark a first starting instruction of the first region with a protection designator, mark a first ending instruction of the first region with a clear designator, and store an amended instruction stream with the markings. The memory execution unit includes circuitry to track the first redundant store based on the protection designator and the clear designator to eliminate the first redundant store.

公开(公告)号：US10228956B2

公开(公告)日：2019-03-12

申请号：US15282266

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Vineeth Mekkat ,  Mark J. Dechene ,  Zhongying Zhang ,  Jason Agron ,  Sebastian Winkel

IPC: G06F9/312 ,  G06F9/44 ,  G06F9/455 ,  G06F9/38 ,  G06F8/41 ,  G06F8/52 ,  G06F9/30

Abstract: In one implementation, a processing device is provided that includes a memory to store instructions and a processor core to execute the instructions. The processor core is to receive a sequence of instructions reordered by a binary translator for execution. A first load of the sequence of instructions is identified. The first load references a memory location that stores a data item to be loaded. An occurrence of a second load is detected. The second load to access the memory location subsequent to an execution of the first load instruction. A protection field in the first load is enabled based on the detected occurrence of the second load. The enabled protection field indicates that the first load is to be checked for an aliasing associated with the memory location with respect to a subsequent store instruction. The second load is eliminated based on the enabled of the protection field.

公开(公告)号：US20180095765A1

公开(公告)日：2018-04-05

申请号：US15282266

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Vineeth Mekkat ,  Mark J. Dechene ,  Zhongying Zhang ,  Jason Agron ,  Sebastian Winkel

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/455 ,  G06F8/443 ,  G06F8/4432 ,  G06F8/4434 ,  G06F8/4435 ,  G06F8/445 ,  G06F8/52 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30181 ,  G06F9/30185 ,  G06F9/3834

Abstract: In one implementation, a processing device is provided that includes a memory to store instructions and a processor core to execute the instructions. The processor core is to receive a sequence of instructions reordered by a binary translator for execution. A first load of the sequence of instructions is identified. The first load references a memory location that stores a data item to be loaded. An occurrence of a second load is detected. The second load to access the memory location subsequent to an execution of the first load instruction. A protection field in the first load is enabled based on the detected occurrence of the second load. The enabled protection field indicates that the first load is to be checked for an aliasing associated with the memory location with respect to a subsequent store instruction. The second load is eliminated based on the enabled of the protection field.

公开(公告)号：US20180074827A1

公开(公告)日：2018-03-15

申请号：US15265587

申请日：2016-09-14

Applicant: Intel Corporation

Inventor： Vineeth Mekkat ,  Youfeng Wu ,  Sebastian Winkel ,  Oleg Margulis

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/0875

Abstract: A processor for redundant stores includes a front end including circuitry to decode instructions from an instruction stream, a data cache unit including circuitry to cache data for the processor, a binary translator, and a memory execution unit. The binary translator includes circuitry to identify a first region of the instruction stream including a redundant store, mark a first starting instruction of the first region with a protection designator, mark a first ending instruction of the first region with a clear designator, and store an amended instruction stream with the markings. The memory execution unit includes circuitry to track the first redundant store based on the protection designator and the clear designator to eliminate the first redundant store.

公开(公告)号：US09710389B2

公开(公告)日：2017-07-18

申请号：US14643354

申请日：2015-03-10

Applicant: INTEL CORPORATION

Inventor： Oleg Margulis ,  Sumit Ahuja ,  Polychronis Xekalakis ,  Yongjun Park ,  Vineeth Mekkat ,  Igor Yanover ,  Sebastian Winkel ,  Ethan Schuchman

IPC: G06F12/06 ,  G06F12/0875 ,  G06F9/38 ,  G06F9/46

CPC classification number: G06F12/0875 ,  G06F9/38 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3855 ,  G06F9/467 ,  G06F2212/1008 ,  G06F2212/452

Abstract: A processor and method are described for alias detection. For example, one embodiment of an apparatus comprises: reordering logic to receive a set of read and write operations in a program order and to responsively reorder the read and write operations; adjustment information attachment logic to associate adjustment information with one or more of the set of read and write operations, wherein for a read operation the adjustment information is to indicate a number of write operations which the read operation has bypassed and for a write operation the adjustment information is to indicate a number of read operations which have bypassed the write operation; and out-of-order processing logic to determine whether execution of the reordered read and write operations will result in a conflict based, at least in part, on the adjustment information associated with the one or more reads and writes.

公开(公告)号：US20160283247A1

公开(公告)日：2016-09-29

申请号：US14668605

申请日：2015-03-25

Applicant: Intel Corporation

Inventor： Girish Venkatasubramanian ,  Ethan Schuchman ,  David Keppel ,  Sebastian Winkel ,  David N. Mackintosh ,  Jaroslaw Topp

IPC: G06F9/38

CPC classification number: G06F9/30087 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/3859 ,  G06F9/3861 ,  G06F9/3863 ,  G06F9/455 ,  G06F9/45516 ,  G06F9/4552

Abstract: Methods and apparatuses relating to selectively executing a commit instruction. In one embodiment, a data storage device stores code that when executed by a hardware processor causes the hardware processor to perform the following: translating an instruction into a translated instruction to be executed by the hardware processor, marking a commit instruction one of for execution and for optional execution by the hardware processor, and including a hint for a commit instruction marked for optional execution; and a hardware commit unit to determine if the commit instruction marked for optional execution is to be executed based on the hint.

Abstract translation: 与选择性地执行提交指令有关的方法和装置。 在一个实施例中，数据存储装置存储当硬件处理器执行时硬件处理器执行以下操作的代码：将指令转换成由硬件处理器执行的转换指令，标记提交指令以执行和 用于硬件处理器的可选执行，并且包括用于可选执行标记的提交指令的提示; 以及硬件提交单元，用于基于提示来确定标记为可选执行的提交指令是否被执行。

公开(公告)号：US20160179538A1

公开(公告)日：2016-06-23

申请号：US14576915

申请日：2014-12-19

Applicant: Intel Corporation

Inventor： JAMISON D. COLLINS ,  Jayesh Iyer ,  Sebastian Winkel ,  Polychronis Xekalakis ,  Howard H. Chen ,  Rupert Brauch

IPC: G06F9/30

CPC classification number: G06F9/30134 ,  G06F8/41 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/384 ,  G06F9/3859 ,  G06F9/3863

Abstract: Embodiments of a method and apparatus for implementing and maintaining a stack of predicate values with stack synchronization instructions. In one embodiment the apparatus is an out of order hardware/software co-designed processor including instructions to explicitly manage the predicate register stack to maintain stack consistency across branches of executing that push a variable number of predicate values onto the predicate stack. In one embodiment the stack-based predicate register implementation enables early branch calculation and early branch misprediction recovery via early renaming of predicate registers.

Abstract translation: 用于使用堆栈同步指令来实现和维护谓词值堆栈的方法和装置的实施例。 在一个实施例中，该装置是一种无序的硬件/软件协同设计的处理器，其包括明确地管理谓词寄存器堆栈以便在执行的分支之间保持堆栈一致性的指令，其将可变数量的谓词值推送到谓词堆栈。 在一个实施例中，基于栈的谓词寄存器实现能够通过早期重命名谓词寄存器来实现早期分支计算和早期分支错误预测恢复。

公开(公告)号：US20160085556A1

公开(公告)日：2016-03-24

申请号：US14494829

申请日：2014-09-24

Applicant: Intel Corporation

Inventor： Sebastian Winkel ,  Ethan Schuchman ,  Tyler Sondag ,  Girish Venkatasubramanian

IPC: G06F9/38

CPC classification number: G06F9/5038 ,  G06F9/30145 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3877 ,  G06F9/4552

Abstract: A processor includes a front end and a scheduler. The front end includes logic to determine whether to apply an acyclical or cyclical thread assignment scheme to code received at the processor, and to, based upon a determined thread assignment scheme, assign code to a static logical thread and to a rotating logical thread. The scheduler includes logic to assign the static logical thread to the same physical thread upon a subsequent control flow execution of the static logical thread, and to assign the rotating logical thread to different physical threads upon different executions of instructions in the rotating logical thread.

Abstract translation: 处理器包括前端和调度器。 前端包括用于确定是否对在处理器处接收到的代码应用非循环或循环线程分配方案的逻辑，以及基于所确定的线程分配方案，将代码分配给静态逻辑线程和旋转逻辑线程。 调度器包括在静态逻辑线程的后续控制流执行时将静态逻辑线程分配给相同物理线程的逻辑，并且在旋转逻辑线程中的指令的不同执行时将旋转逻辑线程分配给不同的物理线程。