公开(公告)号：US20230099724A1

公开(公告)日：2023-03-30

申请号：US17485312

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Elijah V. KARPOV ,  Sou-Chi CHANG ,  Uygar E. AVCI ,  Shriram SHIVARAMAN

IPC: H01L27/11507

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, to memory devices having ferroelectric capacitors coupled between intersecting bitlines and wordlines. Other embodiments may be disclosed or claimed.

公开(公告)号：US20230098467A1

公开(公告)日：2023-03-30

申请号：US17485176

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Carl H. NAYLOR ,  Kirby MAXEY ,  Kevin P. O'BRIEN ,  Chelsey DOROW ,  Sudarat LEE ,  Ashish Verma PENUMATCHA ,  Shriram SHIVARAMAN ,  Uygar E. AVCI ,  Patrick THEOFANIS ,  Charles MOKHTARZADEH ,  Matthew V. METZ ,  Scott B. CLENDENNING

IPC: H01L27/092 ,  H01L29/24 ,  H01L29/06 ,  H01L29/423 ,  H01L29/76 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8256 ,  H01L29/66

Abstract: Thin film transistors having a spin-on two-dimensional (2D) channel material are described. In an example, an integrated circuit structure includes a first device layer including a first two-dimensional (2D) material layer above a substrate. The first 2D material layer includes molybdenum, sulfur, sodium and carbon. A second device layer including a second 2D material layer is above the substrate. The second 2D material layer includes tungsten, selenium, sodium and carbon.

公开(公告)号：US20220149209A1

公开(公告)日：2022-05-12

申请号：US17580550

申请日：2022-01-20

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Aaron LILAK ,  Van H. LE ,  Abhishek A. SHARMA ,  Tahir GHANI ,  Willy RACHMADY ,  Rishabh MEHANDRU ,  Nazila HARATIPOUR ,  Jack T. KAVALIEROS ,  Benjamin CHU-KUNG ,  Seung Hoon SUNG ,  Shriram SHIVARAMAN

IPC: H01L29/786 ,  H01L29/66

Abstract: Thin film transistors having U-shaped features are described. In an example, integrated circuit structure including a gate electrode above a substrate, the gate electrode having a trench therein. A channel material layer is over the gate electrode and in the trench, the channel material layer conformal with the trench. A first source or drain contact is coupled to the channel material layer at a first end of the channel material layer outside of the trench. A second source or drain contact is coupled to the channel material layer at a second end of the channel material layer outside of the trench.

公开(公告)号：US20240006521A1

公开(公告)日：2024-01-04

申请号：US17855620

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Chia-Ching LIN ,  Shriram SHIVARAMAN ,  Kevin P. O'BRIEN ,  Ashish Verma PENUMATCHA ,  Chelsey DOROW ,  Kirby MAXEY ,  Carl H. NAYLOR ,  Sudarat LEE ,  Uygar E. AVCI

IPC: H01L29/775 ,  H01L27/12 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/775 ,  H01L27/1255 ,  H01L29/78391 ,  H01L29/401 ,  H01L29/66969 ,  H01L29/41733 ,  H01L27/1259 ,  H01L29/0673

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques directed to creating back end of line 2D transistors that may be used as access transistors for a memory cell. In embodiments, a combination wet etch and dry etch process may be used to form the 2D transistors. Other embodiments may be described and/or claimed.

公开(公告)号：US20220208778A1

公开(公告)日：2022-06-30

申请号：US17134281

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Nazila HARATIPOUR ,  Sou-Chi CHANG ,  Shriram SHIVARAMAN ,  Jason PECK ,  Uygar E. AVCI ,  Jack T. KAVALIEROS

IPC: H01L27/11514 ,  H01L27/11504 ,  H01L27/11507 ,  G11C7/18 ,  G11C8/14 ,  H01L29/78 ,  H01L29/51 ,  H01L29/66

Abstract: A memory device comprises a series of alternating plate lines and an insulating material over a substrate. Two or more ferroelectric capacitors are through the series of alternating plate lines and an insulating material such that a first one of the ferroelectric capacitors is coupled to a first one of the plate lines and a second one of the ferroelectric capacitors is coupled to a second one of the plate lines. A plurality of substantially parallel bitlines is along a first direction over the two or more ferroelectric capacitors. A plurality of substantially parallel bitlines is along a first direction over the two or more ferroelectric capacitors. A plurality of substantially parallel wordlines is along a second direction orthogonal to the first direction over the two or more ferroelectric capacitors. An access transistor is located over and controls the two or more ferroelectric capacitors, the access transistor incorporating a first one of the bitlines and a first one of the wordlines. The bitline comprise a first source/drain of a source/drain pair, and a second source/drain is aligned, and in contact, with a top one of the two or more ferroelectric capacitors, and the first wordline forms a gate of the access transistor.

公开(公告)号：US20210408288A1

公开(公告)日：2021-12-30

申请号：US16913835

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Carl NAYLOR ,  Chelsey DOROW ,  Kirby MAXEY ,  Tanay GOSAVI ,  Ashish Verma PENUMATCHA ,  Shriram SHIVARAMAN ,  Chia-Ching LIN ,  Sudarat LEE ,  Uygar E. AVCI

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/24 ,  H01L29/66

Abstract: Embodiments disclosed herein comprise semiconductor devices with two dimensional (2D) semiconductor channels and methods of forming such devices. In an embodiment, the semiconductor device comprises a source contact and a drain contact. In an embodiment, a 2D semiconductor channel is between the source contact and the drain contact. In an embodiment, the 2D semiconductor channel is a shell.

公开(公告)号：US20200343379A1

公开(公告)日：2020-10-29

申请号：US16634517

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： Abhishek A. SHARMA ,  Van H. LE ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Gilbert DEWEY ,  Shriram SHIVARAMAN ,  Inanc MERIC ,  Benjamin CHU-KUNG

IPC: H01L29/786 ,  H01L29/51 ,  H01L27/108 ,  H01L27/24 ,  H01L29/66

Abstract: Embodiments herein describe techniques for a semiconductor device, which may include a substrate, a metallic encapsulation layer above the substrate, and a gate electrode above the substrate and next to the metallic encapsulation layer. A channel layer may be above the metallic encapsulation layer and the gate electrode, where the channel layer may include a source area and a drain area. In addition, a source electrode may be coupled to the source area, and a drain electrode may be coupled to the drain area. Other embodiments may be described and/or claimed.

公开(公告)号：US20200312973A1

公开(公告)日：2020-10-01

申请号：US16651955

申请日：2017-12-21

Applicant: Intel Corporation

Inventor： Sean T. MA ,  Abhishek SHARMA ,  Gilbert DEWEY ,  Van H. LE ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Benjamin CHU-KUNG ,  Shriram SHIVARAMAN

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/786

Abstract: This disclosure illustrates a transistor with dual gate workfunctions. The transistor with dual gate workfunctions may comprise a source region, a drain region, a channel between the source region and the drain region, and a gate to control a conductivity of the channel. The gate may comprise a first portion with a first workfunction and a second portion with a second workfunction. One of the portions is nearer the source region than the other portion. The workfunction of the portion nearer the source provides a lower thermionic barrier than the workfunction of the portion further away from the source.

公开(公告)号：US20200227568A1

公开(公告)日：2020-07-16

申请号：US16638301

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Van H. LE ,  Abhishek A. SHARMA ,  Benjamin CHU-KUNG ,  Gilbert DEWEY ,  Ravi PILLARISETTY ,  Miriam R. RESHOTKO ,  Shriram SHIVARAMAN ,  Li Huey TAN ,  Tristan A. TRONIC ,  Jack T. KAVALIEROS

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/417 ,  H01L29/40

Abstract: Embodiments herein describe techniques for a semiconductor device, which may include a substrate, and a U-shaped channel above the substrate. The U-shaped channel may include a channel bottom, a first channel wall and a second channel wall parallel to each other, a source area, and a drain area. A gate dielectric layer may be above the substrate and in contact with the channel bottom. A gate electrode may be above the substrate and in contact with the gate dielectric layer. A source electrode may be coupled to the source area, and a drain electrode may be coupled to the drain area. Other embodiments may be described and/or claimed.

公开(公告)号：US20200066912A1

公开(公告)日：2020-02-27

申请号：US16325164

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Van H. LE ,  Rafael RIOS ,  Shriram SHIVARAMAN ,  Jack T. KAVALIEROS ,  Marko RADOSAVLJEVIC

IPC: H01L29/786 ,  H01L29/221 ,  H01L29/66

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing bi-layer semiconducting oxides in a source/drain for low access and contact resistance of thin film transistors. For instance, there is disclosed in accordance with one embodiment a semiconductor device having therein a substrate; a bi-layer oxides layer formed from a first oxide material and a second oxide material, the first oxide material comprising a semiconducting oxide material and having different material properties from the second oxide material comprising a high mobility oxide material; a channel layer formed atop the substrate, the channel layer formed from the semiconducting oxide material of the bi-layer oxides layer; a high mobility oxide layer formed atop the channel layer, the high conductivity oxide layer formed from the high mobility oxide material of the bi-layer oxides layer; metallic contacts formed atop the high mobility oxide layer; a gate and a gate oxide material formed atop the high mobility oxide layer, the gate oxide material being in direct contact with the high mobility oxide layer; and spacers separating the metallic contacts from the gate and gate oxide material. Other related embodiments are disclosed.