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    SECURE ERROR HANDLING
    21.
    发明申请
    SECURE ERROR HANDLING 有权
    安全错误处理

    公开(公告)号：US20140237299A1

    公开(公告)日：2014-08-21

    申请号：US13997301

    申请日：2011-12-29

    Applicant: INTEL CORPORATION

    Inventor： Murugasamy Nachimuthu ,  Mohan J. Kumar ,  Theodros Yigzaw ,  Jose A. Vargas ,  Rajendra Kuramkote

    IPC: G06F11/07

    CPC classification number: G06F11/0772 ,  G06F11/0745 ,  G06F11/3664 ,  G06F21/57

    Abstract: Various embodiments are described herein. Some embodiments include an Operating System and a platform. The platform includes a processor having an error register. The Operating System can write to the error register only via the platform in a secure manner (for example, using platform firmware). Other embodiments are described and claimed.

    Abstract translation: 本文描述了各种实施例。 一些实施例包括操作系统和平台。 该平台包括具有错误寄存器的处理器。 操作系统只能通过平台以安全的方式（例如使用平台固件）写入错误寄存器。 描述和要求保护其他实施例。

    Device, system, and method to concurrently store multiple PMON counts in a single register
    22.
    发明授权
    Device, system, and method to concurrently store multiple PMON counts in a single register 有权

    公开(公告)号：US12044730B2

    公开(公告)日：2024-07-23

    申请号：US17131477

    申请日：2020-12-22

    Applicant: Intel Corporation

    Inventor： Gaurav Porwal ,  Subhankar Panda ,  Theodros Yigzaw ,  John Holm

    IPC: G01R31/28 ,  G01R31/317

    CPC classification number: G01R31/317

    Abstract: Techniques and mechanisms for providing performance monitoring information. In an embodiment, a performance monitor circuit receives a communication which indicates a format comprising multiple fields which are each to store a respective count of monitored events. A programming of the performance monitor circuit, based on the communication, designates first bits and second bits of the register to provide, respectively, a first first field and a second field according to the format. Performance monitoring subsequent to the programming successively tallies a first count of first events which occur during a first period of time, and a second count of second events which occur during a second period of time. In another embodiment, performance monitoring results in the register concurrently storing both the first count and the second count.

    Hardware unit for reverse translation in a processor
    24.
    发明授权
    Hardware unit for reverse translation in a processor 有权

    公开(公告)号：US11307996B2

    公开(公告)日：2022-04-19

    申请号：US16206516

    申请日：2018-11-30

    Applicant: Intel Corporation

    Inventor： Sarathy Jayakumar ,  Ashok Raj ,  Wei P. Chen ,  Theodros Yigzaw ,  John Holm

    IPC: G06F12/1027 ,  G06F12/0864 ,  G06F13/16 ,  G06F11/22 ,  G06F9/38

    Abstract: In an embodiment, a processor for reverse translation includes a plurality of processing engines (PEs) to execute threads and a reverse translation circuit. The reverse translation circuit is to: determine a target module address of a corrupt portion of a memory module; determine a plurality of system physical address (SPA) addresses associated with the memory module; and for each SPA address in the plurality of SPA addresses, translate the SPA address into a translated module address, and in response to a determination that the translated module address matches the target module address, log the SPA address as a result of a reverse translation of the target module address. Other embodiments are described and claimed.

    System and method to increase availability in a multi-level memory configuration
    27.
    发明授权
    System and method to increase availability in a multi-level memory configuration 有权

    公开(公告)号：US10324852B2

    公开(公告)日：2019-06-18

    申请号：US15374796

    申请日：2016-12-09

    Applicant: INTEL CORPORATION

    Inventor： Theodros Yigzaw ,  Ashok Raj ,  Robert C. Swanson ,  Mohan J. Kumar

    IPC: G06F11/00 ,  G06F12/0868 ,  G06F11/20 ,  G06F12/109

    Abstract: One embodiment provides for a data processing system comprising a multi-level system memory including a first memory level of volatile memory and a second memory level that is larger and slower in comparison with the first memory level. The second memory level includes non-volatile memory and can additionally include volatile memory. The multi-level system memory includes a multi-level memory controller including logic to manage a list of faulty addresses within the multi-level system memory. The multi-level memory controller can manage a list of faulty addresses. The multi-level memory controller is configured to satisfy a request for data stored in the first memory level from the second memory level when the data is stored in an address on the list of faulty addresses.

    Enabling error status and reporting in a machine check architecture
    28.
    发明授权
    Enabling error status and reporting in a machine check architecture 有权

    公开(公告)号：US10318368B2

    公开(公告)日：2019-06-11

    申请号：US15168999

    申请日：2016-05-31

    Applicant: Intel Corporation

    Inventor： Ashok Raj ,  Theodros Yigzaw

    IPC: G06F11/00 ,  G06F11/07

    Abstract: In accordance with implementations disclosed herein, there is provided systems and methods for enabling error status and reporting in a machine check environment. A processing device includes an error status register and an error status component communicably coupled to the error status register. The error status component determines that a machine check error (MCE) is a first correctable error (CE) and sets a first error status corresponding to the first CE in the error status register based on a threshold value. The threshold value is based on a type of the first CE.

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