-
公开(公告)号：US10298117B2
公开(公告)日：2019-05-21
申请号：US15638643
申请日：2017-06-30
Applicant: INTEL CORPORATION
Inventor： Harish Krishnamurthy , Khondker Ahmed , Vivek De , Nachiket Desai , Suhwan Kim , Xiaosen Liu , Turbo Majumder , Krishnan Ravichandran , Christopher Schaef , Vaibhav Vaidya , Sriram Vangal
Abstract: Embodiments described herein describe operating a master-slave controller. Operating the master-slave controller comprises, based on a determination that the first output voltage value is greater than the second output voltage value, calculating a first duty cycle value and an input voltage value and the second voltage regulator, calculating a second duty cycle value based on the first duty cycle value, and based on a determination that the second output voltage value is greater than or equal to the first output voltage value, calculating the second duty cycle value based on the second output voltage value and the input voltage value and calculating the first duty cycle value based on the second duty cycle value and configuring the first voltage regulator with the first duty cycle value and the second voltage regulator with the second duty cycle value.
-
公开(公告)号：US20190064907A1
公开(公告)日：2019-02-28
申请号：US15682724
申请日：2017-08-22
Applicant: Intel Corporation
Inventor： Dileep J. Kurian , Ankit Gupta , Akhila M , Tanay Karnik , Vaibhav Vaidya , David Arditti Ilitzky , Christopher Schaef , Sriram Kabisthalam Muthukumar , Harish K. Krishnamurthy , Suhwan Kim
IPC: G06F1/32
Abstract: Systems, apparatuses and methods may provide for early pre-charge with respect to peak power events. Application performance may improve by pre-charging a supercap just prior to initiating a system wake up from a qualified system wake-source trigger. Additionally, the pre-charging of the supercap may be controlled by a time defined pre-charge period and may also be controlled by a predetermined threshold voltage.
-
公开(公告)号：US20180375433A1
公开(公告)日：2018-12-27
申请号：US15632086
申请日：2017-06-23
Applicant: INTEL CORPORATION
Inventor： Khondker Ahmed , Vivek De , Nachiket Desai , Suhwan Kim , Harish Krishnamurthy , Xiaosen Liu , Turbo Majumder , Krishnan Ravichandran , Christopher Schaef , Vaibhav Vaidya , Sriram Vangal
CPC classification number: H02M3/1582 , G05F1/67 , H02M1/08 , H02M2001/0003 , H02M2001/0009 , H02M2001/0025
Abstract: Embodiments described herein concern operating a peak-delivered-power (PDP) controller. Operating a PDP includes calculating the new power output value from the output voltage value and the output current value, determining whether the new power output value is greater than the previous power output value to determine whether the voltage regulator is outputting a maximum power output, based on a determination that the new power output value is greater than the previous power output value, providing an instruction to a duty generator to increase a duty cycle of the voltage regulator, based on a determination that the new power output value is not greater than the previous power output value, providing an instruction to the duty generator to decrease the duty cycle of the voltage regulator, and replacing the previous power output value with the new power output value.
-
公开(公告)号：US09958922B2
公开(公告)日：2018-05-01
申请号：US15589656
申请日：2017-05-08
Applicant: Intel Corporation
Inventor： George E. Matthew , Rinkle Jain , Vaibhav Vaidya
CPC classification number: G06F1/28 , G05F1/10 , G05F1/32 , G05F1/40 , G05F3/08 , G06F1/26 , G06F1/305 , H02M1/088 , H02M3/07 , H02M3/156 , H02M2001/0003
Abstract: Methods and apparatus relating to a low ripple mechanism of mode change in switched capacitor voltage regulators are described. In an embodiment, a mode change of a Switching Capacitor Voltage Regulator (SCVR) is caused based at least in part on a comparison of an output voltage of the SCVR and a reference voltage. The output voltage is sensed based at least in part on a clock signal. Other embodiments are also disclosed and claimed.
-
公开(公告)号：US20170242468A1
公开(公告)日：2017-08-24
申请号：US15589656
申请日：2017-05-08
Applicant: Intel Corporation
Inventor： George E. Matthew , Rinkle Jain , Vaibhav Vaidya
CPC classification number: G06F1/28 , G05F1/10 , G05F1/32 , G05F1/40 , G05F3/08 , G06F1/26 , G06F1/305 , H02M1/088 , H02M3/07 , H02M3/156 , H02M2001/0003
Abstract: Methods and apparatus relating to a low ripple mechanism of mode change in switched capacitor voltage regulators are described. In an embodiment, a mode change of a Switching Capacitor Voltage Regulator (SCVR) is caused based at least in part on a comparison of an output voltage of the SCVR and a reference voltage. The output voltage is sensed based at least in part on a clock signal. Other embodiments are also disclosed and claimed.
-
Patent Agency Ranking
公开(公告)号：US09680363B2
公开(公告)日：2017-06-13
申请号：US14866662
申请日：2015-09-25
Applicant: Intel Corporation
Inventor： George E. Matthew , Rinkle Jain , Vaibhav Vaidya
CPC classification number: G06F1/28 , G05F1/10 , G05F1/32 , G05F1/40 , G05F3/08 , G06F1/26 , G06F1/305 , H02M1/088 , H02M3/07 , H02M3/156 , H02M2001/0003
Abstract: Methods and apparatus relating to a low ripple mechanism of mode change in switched capacitor voltage regulators are described. In an embodiment, a mode change of a Switching Capacitor Voltage Regulator (SCVR) is caused based at least in part on a comparison of an output voltage of the SCVR and a reference voltage. The output voltage is sensed based at least in part on a clock signal. Other embodiments are also disclosed and claimed.
-
公开(公告)号：US20160231761A1
公开(公告)日：2016-08-11
申请号：US15133177
申请日：2016-04-19
Applicant: Intel Corporation
Inventor： Rinkle Jain , Yi-Chun Shih , Vaibhav Vaidya
IPC: G05F1/56
Abstract: Described is an apparatus comprising: an output stage having an input supply node to receive an input power supply and an output node to provide an output supply to a load; an amplifier to control current strength of the output stage according to the output supply and a reference voltage; and a hysteresis unit to monitor the output supply and operable to control the current strength of the output stage according to a voltage level of the output supply. Described is another apparatus which comprises: a plurality of charge pumps to adjust current strength of the output stage; and a logic unit to monitor the output supply and operable to control the plurality of charge pumps according to a voltage level of the output supply and one or more reference voltages.
Abstract translation: 描述了一种装置，包括：输出级，其具有用于接收输入电源的输入电源节点和向负载提供输出电源的输出节点; 放大器，用于根据输出电源和参考电压来控制输出级的电流强度; 以及滞后单元，用于监视输出电源并且可操作以根据输出电源的电压电平来控制输出级的电流强度。 描述了另一种装置，其包括：多个电荷泵，用于调节输出级的电流强度; 以及逻辑单元，用于监视输出电源并可操作以根据输出电源的电压电平和一个或多个参考电压来控制多个电荷泵。
-
公开(公告)号：US11411491B2
公开(公告)日：2022-08-09
申请号：US16642853
申请日：2017-09-29
Applicant: Intel Corporation
Inventor： Vivek De , Krishnan Ravichandran , Harish Krishnamurthy , Khondker Ahmed , Sriram Vangal , Vaibhav Vaidya , Turbo Majumder , Christopher Schaef , Suhwan Kim , Xiaosen Liu , Nachiket Desai
Abstract: Voltage dividing circuitry is provided for use in a voltage converter for converting at least one input Direct Current, DC voltage to a plurality of output DC voltages. The voltage dividing circuitry including a voltage input port to receive an input DC voltage and an inductor having an input-side switch node and an output-side switch node. The output side switch node is connectable to one of a plurality of voltage output ports to supply a converted value of the input DC voltage as an output DC voltage. The flying capacitor interface has a plurality of switching elements and at least one flying capacitor, the flying capacitor interface to divide the input DC voltage to provide a predetermined fixed ratio of the input DC voltage at the input-side switch node of the inductor. A voltage converter and a power management integrated circuit having the voltage dividing circuitry are also provided.
-
公开(公告)号：US20190199206A1
公开(公告)日：2019-06-27
申请号：US15855683
申请日：2017-12-27
Applicant: INTEL CORPORATION
Inventor： Christopher Schaef , Vaibhav Vaidya , Suhwan Kim
Abstract: In some examples, an apparatus for reference voltage generation includes a plurality of reference voltage rails each with a corresponding reference voltage, a first controller, and a second controller. The first controller is to cycle through the plurality of reference voltage rails and maintain the reference voltages in a synchronous mode. The second controller is to detect an event and provide an indication to the first controller to update in an asynchronous mode one of the plurality of reference voltages in response to the event. The first controller is to update in an asynchronous mode the one of the plurality of reference voltages in response to the event.
-
30.发明申请公开(公告)号：US20190190725A1
公开(公告)日：2019-06-20
申请号：US15846045
申请日：2017-12-18
Applicant: Intel Corporation
Inventor： Vivek De , Krishnan Ravichandran , Harish Krishnamurthy , Khondker Ahmed , Sriram Vangal , Vaibhav Vaidya , Turbo Majumder , Christopher Schaef , Suhwan Kim , Xiaosen Liu , Nachiket Desai
IPC: H04L9/32
CPC classification number: H04L9/3278
Abstract: An apparatus is provided which comprises: an array of physically unclonable function (PUF) devices, wherein an individual device of the array comprises a magnetic junction and an interconnect, wherein the interconnect comprises a spin orbit coupling material; a circuitry to sense values stored in the array, and to provide an output; and a comparator to compare the output with a code.
-
-
-
-
-
-
-
-
-
Search Results
38
records
(took 0.021 seconds)
