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    VOLTAGE MODULATED CONTROL LANE
    22.
    发明申请
    VOLTAGE MODULATED CONTROL LANE 审中-公开

    公开(公告)号：US20180095925A1

    公开(公告)日：2018-04-05

    申请号：US15283028

    申请日：2016-09-30

    Applicant: Intel Corporation

    Inventor： Venkatraman Iyer ,  Zuoguo Wu ,  Mahesh Wagh

    IPC: G06F13/42 ,  G06F1/26

    CPC classification number: G06F13/4265 ,  G06F1/3253 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A computing component is provided with physical layer logic to receive data on a physical link including a plurality of lanes, where the data is received from a particular component on one or more data lanes of the physical link. The physical layer is further to receive a stream signal on a particular one of the plurality of lanes of the physical link, where the stream signal is to identify a type of the data on the one or more data lanes, the type is one of a plurality of different types supported by the particular component, and the stream signal is encoded through voltage amplitude modulation on the particular lane.

    High performance optical repeater
    24.
    发明授权
    High performance optical repeater 有权
    高性能光中继器

    公开(公告)号：US09444551B2

    公开(公告)日：2016-09-13

    申请号：US14577979

    申请日：2014-12-19

    Applicant: Intel Corporation

    Inventor： Jing Fang ,  Zuoguo Wu ,  Venkatraman Iyer

    IPC: H04B10/29 ,  H04B10/2575

    CPC classification number: H04B10/29 ,  H04B10/2575

    Abstract: An optical element is to be coupled to a second device by the second electrical link. The particular optical element is further to receive a first signal from the second device over a first inbound lane of the second electrical link, receive a second signal from the second device over a second inbound lane of the second electrical link, and multiplex the first and second signals on a particular optical link to send the first and second signals to the first device.

    Abstract translation: 光学元件将通过第二电连接件耦合到第二装置。 所述特定光学元件还用于通过所述第二电连接的第一入口通道从所述第二设备接收第一信号，在所述第二电连接的第二入站通道上从所述第二设备接收第二信号，并且将所述第一和第 在特定光链路上的第二信号以将第一和第二信号发送到第一设备。

    COMPLIANCE AND DEBUG TESTING OF A DIE-TO-DIE INTERCONNECT
    27.
    发明申请
    COMPLIANCE AND DEBUG TESTING OF A DIE-TO-DIE INTERCONNECT 有权

    公开(公告)号：US20220318111A1

    公开(公告)日：2022-10-06

    申请号：US17844348

    申请日：2022-06-20

    Applicant: Intel Corporation

    Inventor： Swadesh Choudhary ,  Narasimha Lanka ,  Debendra Das Sharma ,  Lakshmipriya Seshan ,  Zuoguo Wu ,  Gerald Pasdast

    IPC: G06F11/263 ,  G06F13/42

    Abstract: In one embodiment, an apparatus comprises a first die that includes: a die-to-die adapter comprising a plurality of first registers, the die-to-die adapter to communicate with protocol layer circuitry via a flit-aware die-to-die interface (FDI) and physical layer circuitry via a raw die-to-die interface (RDI), wherein the die-to-die adapter is to receive message information of a first interconnect protocol; and the physical layer circuitry coupled to the die-to-die adapter, the physical layer circuity comprising a plurality of second registers, where the physical layer circuitry is to receive and output the message information to a second die via an interconnect having a mainband and a sideband. During a test of the apparatus, the sideband is to enable access to information in at least one of the plurality of first registers or at least one of the plurality of second registers. Other embodiments are described and claimed.

    EXTENDING MULTICHIP PACKAGE LINK OFF PACKAGE
    28.
    发明申请
    EXTENDING MULTICHIP PACKAGE LINK OFF PACKAGE 有权

    公开(公告)号：US20210097015A1

    公开(公告)日：2021-04-01

    申请号：US17121534

    申请日：2020-12-14

    Applicant: Intel Corporation

    Inventor： Debendra Das Sharma ,  Zuoguo Wu ,  Mahesh Wagh ,  Mohiuddin M. Mazumder ,  Venkatraman Iyer ,  Jeff C. Morriss

    IPC: G06F13/40 ,  H01L23/538 ,  H01L25/065 ,  G06F13/42

    Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.

    APPROXIMATE DATA BUS INVERSION TECHNIQUE FOR LATENCY SENSITIVE APPLICATIONS
    29.
    发明申请
    APPROXIMATE DATA BUS INVERSION TECHNIQUE FOR LATENCY SENSITIVE APPLICATIONS 有权

    公开(公告)号：US20210004347A1

    公开(公告)日：2021-01-07

    申请号：US17029288

    申请日：2020-09-23

    Applicant: Intel Corporation

    Inventor： Narasimha Lanka ,  Lakshmipriya Seshan ,  Gerald S. Pasdast ,  Zuoguo Wu

    IPC: G06F13/42 ,  G06F13/40

    Abstract: Systems, methods, and apparatuses associated with an approximate majority based data bus inversion technique are disclosed. A method comprises obtaining, at a first device connected by a plurality of lanes to a second device, original data comprising first bits and second bits, where the first bits are to be transmitted in a new clock cycle via first lanes of the plurality of lanes, and the second bits are to be transmitted in the new clock cycle via second lanes of the plurality of lanes. The method further includes determining whether a first criterion associated with the first bits is met, determining whether a second criterion associated with the second bits is met, and transmitting an inverted version of the original data via the plurality of lanes based, at least in part, on determining that the first criterion and the second criterion are met.

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