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    DEVICE DESIGN FOR PARTIALLY ORIENTED RUTILE DIELECTRICS
    21.
    发明申请
    DEVICE DESIGN FOR PARTIALLY ORIENTED RUTILE DIELECTRICS 有权
    器件设计用于局部方向的电介质

    公开(公告)号：US20140191365A1

    公开(公告)日：2014-07-10

    申请号：US13738127

    申请日：2013-01-10

    Applicant: INTERMOLECULAR, INC.

    Inventor： Sergey Barabash ,  Dipankar Pramanik

    IPC: H01L49/02

    CPC classification number: H01L28/40 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/31122 ,  H01L28/91

    Abstract: Methods include forming a dielectric layer from a first material above a substrate. The dielectric layer is formed such that a preferred crystal direction for at least one electrical property of the first material is parallel to a surface of the dielectric layer. Next, forming a first and second trench within the dielectric layer wherein the first and second trenches have at least one curved portion. Forming a second material within the first trench and a third material within the second trench wherein the first material is different from the second and third materials. The first and second trenches are separated by a distance between 3-20 nm.

    Abstract translation: 方法包括从衬底上的第一材料形成电介质层。 电介质层形成为使得第一材料的至少一个电性能的优选晶体方向平行于电介质层的表面。 接下来，在电介质层内形成第一和第二沟槽，其中第一和第二沟槽具有至少一个弯曲部分。 在第一沟槽内形成第二材料，在第二沟槽内形成第三材料，其中第一材料与第二和第三材料不同。 第一和第二沟槽间隔3-20nm的距离。

    Device design for partially oriented rutile dielectrics
    22.
    发明授权
    Device design for partially oriented rutile dielectrics 有权
    部分定向金红石电介质的器件设计

    公开(公告)号：US08766404B1

    公开(公告)日：2014-07-01

    申请号：US13738127

    申请日：2013-01-10

    Applicant: Intermolecular, Inc.

    Inventor： Sergey Barabash ,  Dipankar Pramanik

    IPC: H01L21/02 ,  H01L21/20 ,  H01L29/66 ,  H01L29/94 ,  H01L49/02

    CPC classification number: H01L28/40 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/31122 ,  H01L28/91

    Abstract: Methods include forming a dielectric layer from a first material above a substrate. The dielectric layer is formed such that a preferred crystal direction for at least one electrical property of the first material is parallel to a surface of the dielectric layer. Next, forming a first and second trench within the dielectric layer wherein the first and second trenches have at least one curved portion. Forming a second material within the first trench and a third material within the second trench wherein the first material is different from the second and third materials. The first and second trenches are separated by a distance between 3-20 nm.

    Abstract translation: 方法包括从衬底上的第一材料形成电介质层。 电介质层形成为使得第一材料的至少一个电性能的优选晶体方向平行于电介质层的表面。 接下来，在电介质层内形成第一和第二沟槽，其中第一和第二沟槽具有至少一个弯曲部分。 在第一沟槽内形成第二材料，在第二沟槽内形成第三材料，其中第一材料与第二和第三材料不同。 第一和第二沟槽间隔3-20nm的距离。

    Method of Depositing Films with Narrow-Band Conductive Properties
    23.
    发明申请
    Method of Depositing Films with Narrow-Band Conductive Properties 有权
    沉积具有窄带导电性能的薄膜的方法

    公开(公告)号：US20140175567A1

    公开(公告)日：2014-06-26

    申请号：US13722931

    申请日：2012-12-20

    Applicant: INTERMOLECULAR, INC.

    Inventor： Sergey Barabash ,  Dipankar Pramanik

    IPC: H01L21/3065 ,  H01L29/78

    CPC classification number: H01L29/78 ,  H01L21/28255 ,  H01L21/3105 ,  H01L21/76823 ,  H01L21/76826

    Abstract: Conducting materials having narrow impurity conduction bands can reduce the number of high energy excitations, and can be prepared by a sequence of plasma treatments. For example, a dielectric layer can be exposed to a first plasma ambient to form vacancy sites, and the vacancy-formed dielectric layer can be subsequently exposed to a second plasma ambient to fill the vacancy sites with substitutional impurities.

    Abstract translation: 具有窄杂质导带的导电材料可以减少高能量激发的数量，并且可以通过一系列等离子体处理来制备。 例如，电介质层可以暴露于第一等离子体环境以形成空位，并且随后将空位形成的电介质层暴露于第二等离子体环境以用替代杂质填充空位。

    Superconducting circuits with reduced microwave absorption
    26.
    发明授权
    Superconducting circuits with reduced microwave absorption 有权
    具有减少微波吸收的超导电路

    公开(公告)号：US09455073B2

    公开(公告)日：2016-09-27

    申请号：US14259455

    申请日：2014-04-23

    Applicant: Intermolecular, Inc. ,  Northrop Grumman Systems Corporation

    Inventor： Sergey Barabash ,  Dipankar Pramanik ,  Andrew Steinbach ,  Chris Kirby

    IPC: H01B12/02 ,  H01L39/24 ,  H01L39/22

    CPC classification number: H01B12/02 ,  H01L39/22 ,  H01L39/24 ,  Y10S505/704 ,  Y10S505/706

    Abstract: Provided are superconducting circuits, methods of operating these superconducting circuits, and methods of determining processing conditions for operating these superconducting circuits. A superconducting circuit includes a superconducting element, a conducting element, and a dielectric element disposed between the superconducting element and the conducting element. The conducting element may be another superconducting element, a resonating element, or a conducting casing. During operation of the superconducting element a direct current (DC) voltage is applied between the superconducting element and the conducting element. This application of the DC voltage reduces average microwave absorption of the dielectric element. In some embodiments, when the DC voltage is first applied, the microwave absorption may initially rise and then fall below the no-voltage absorption level. The DC voltage level may be determined by testing the superconducting circuit at different DC voltage levels and selecting the one with the lowest microwave absorption.

    Abstract translation: 提供超导电路，操作这些超导电路的方法以及确定用于操作这些超导电路的处理条件的方法。 超导电路包括超导元件，导电元件和设置在超导元件和导电元件之间的介电元件。 导电元件可以是另一种超导元件，谐振元件或导电壳体。 在超导元件的操作期间，在超导元件和导电元件之间施加直流（DC）电压。 DC电压的这种应用降低了介电元件的平均微波吸收。 在一些实施例中，当首先施加DC电压时，微波吸收可以最初升高然后降低到无电压吸收水平以下。 直流电压电平可以通过在不同的直流电压电平下测试超导电路并选择具有最低微波吸收的电路来确定。

    Hydrogenated Amorphous Silicon Dielectric for Superconducting Devices
    27.
    发明申请
    Hydrogenated Amorphous Silicon Dielectric for Superconducting Devices 有权
    用于超导器件的氢化非晶硅介质

    公开(公告)号：US20150184286A1

    公开(公告)日：2015-07-02

    申请号：US14145337

    申请日：2013-12-31

    Applicant: Intermolecular, Inc.

    Inventor： Sergey Barabash ,  Dipankar Pramanik ,  Andrew Steinbach

    IPC: C23C16/24 ,  C23C14/14 ,  C23C14/34 ,  C23C14/48 ,  C23C16/56

    CPC classification number: C23C16/24 ,  C23C14/14 ,  C23C14/5806 ,  C23C14/5826 ,  C23C14/5846 ,  C23C16/56 ,  H01J37/32357 ,  H01J37/32917 ,  H01J37/32935 ,  H01J37/3405

    Abstract: Amorphous silicon (a-Si) is hydrogenated for use as a dielectric (e.g., an interlayer dielectric) for superconducting electronics. A hydrogenated a-Si layer is formed on a substrate by CVD or sputtering. The hydrogen may be integrated during or after the a-Si deposition. After the layer is formed, it is first annealed in an environment of high hydrogen chemical potential and subsequently annealed in an environment of low hydrogen chemical potential. Optionally, the a-Si (or an H-permeable overlayer, if added) may be capped with a hydrogen barrier before removing the substrate from the environment of low hydrogen chemical potential.

    Abstract translation: 非晶硅（a-Si）被氢化用作超导电子器件的电介质（例如，层间电介质）。 通过CVD或溅射在衬底上形成氢化a-Si层。 在a-Si沉积期间或之后，氢可以被整合。 在形成层之后，首先在高氢化学势的环境中退火，随后在低氢化学势的环境中退火。 任选地，在从低氢化学势的环境中除去衬底之前，可以用氢气阻挡层将a-Si（或者如果加入的是H-可渗透的覆盖层）封盖。

    Controlling ReRam Forming Voltage with Doping
    28.
    发明申请
    Controlling ReRam Forming Voltage with Doping 审中-公开
    用掺杂控制ReRam成型电压

    公开(公告)号：US20150064873A1

    公开(公告)日：2015-03-05

    申请号：US14527276

    申请日：2014-10-29

    Applicant: Intermolecular, Inc.

    Inventor： Sergey Barabash ,  Charlene Chen ,  Dipankar Pramanik

    IPC: H01L45/00

    CPC classification number: H01L45/1616 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1641

    Abstract: An internal electrical field in a resistive memory element can be formed to reduce the forming voltage. The internal electric field can be formed by incorporating one or more charged layers within the switching dielectric layer of the resistive memory element. The charged layers can include adjacent charge layers to form dipole layers. The charged layers can be formed at or near the interface of the switching dielectric layer with an electrode layer. Further, the charged layer can be oriented with lower valence substitution side towards lower work function electrode, and higher valence substitution side towards higher work function electrode.

    Abstract translation: 可以形成电阻式存储元件中的内部电场以降低成形电压。 可以通过在电阻式存储元件的开关电介质层内并入一个或多个带电层来形成内部电场。 带电层可以包括相邻的电荷层以形成偶极层。 带电层可以在开关电介质层的界面处或附近形成电极层。 此外，带电层可以朝向较低功函电极的较低价取代面取向，而朝较高功函电极取向较高的取代价。

    Two step deposition of molybdenum dioxide electrode for high quality dielectric stacks
    30.
    发明授权
    Two step deposition of molybdenum dioxide electrode for high quality dielectric stacks 有权
    二级沉积二氧化钼电极用于高质量电介质叠层

    公开(公告)号：US08835310B2

    公开(公告)日：2014-09-16

    申请号：US13725701

    申请日：2012-12-21

    Applicant: Intermolecular, Inc.

    Inventor： Sergey Barabash ,  Dipankar Pramanik ,  Xuena Zhang

    IPC: H01L21/4763 ,  H01L49/02

    CPC classification number: H01L28/55 ,  C23C14/083 ,  C23C14/5806 ,  H01L21/28088 ,  H01L21/32051 ,  H01L28/40 ,  H01L28/60 ,  H01L29/4966 ,  H01L29/785

    Abstract: Electrodes, which contain molybdenum dioxide (MoO2) can be used in electronic components, such as memory or logic devices. The molybdenum-dioxide containing electrodes can also have little or no molybdenum element, together with a portion of molybdenum oxide, e.g., MoOx with x between 2 and 3. The molybdenum oxide can be present as molybdenum trioxide MoO3, or in Magneli phases, such as Mo4O11, MO8O23, or Mo9O26. The molybdenum-dioxide containing electrodes can be formed by annealing a multilayer including a layer of molybdenum and a layer of molybdenum oxide. The oxygen content of the multilayer can be configured to completely, or substantially completely, react with molybdenum to form molybdenum dioxide, together with leaving a small excess amount of molybdenum oxide MoOx with x>2.

    Abstract translation: 含有二氧化钼（MoO2）的电极可用于电子元件，如存储器或逻辑器件。 含有二氧化钼的电极也可以具有很少的或没有钼元素，以及一部分氧化钼，例如Mo 2 x，x在2和3之间。氧化钼可以以三氧化钼MoO 3或Magneli相存在，例如 如Mo4O11，MO8O23或Mo9O26。 含二氧化钼的电极可以通过将包含钼层和氧化钼层的多层退火而形成。 多层的氧含量可以被配置为完全或基本完全地与钼反应形成二氧化钼，同时留下少量过量的x> 2的氧化钼MoO x。

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