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公开(公告)号：US10229738B2
公开(公告)日：2019-03-12
申请号：US15496114
申请日：2017-04-25
IPC分类号： G11C14/00 , G11C13/00 , G11C11/419 , G11C29/12
摘要： Embodiments include techniques for static random access memory (SRAM) bitline equalization using phase change material (PCM). The techniques include detecting a defect in SRAM bitlines, and programming a variable resistance PCM cell to offset the detected defect. The techniques also include measuring signal development time for the SRAM bitlines, and adjusting the programming of the variable resistance PCM cell based at least in part on the measured signal development for the SRAM bitlines.
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22.发明授权公开(公告)号：US10168923B2
公开(公告)日：2019-01-01
申请号：US15138629
申请日：2016-04-26
IPC分类号： G06F3/06 , G11C11/4096 , G11C11/406 , G06F11/20 , G11C14/00 , G11C5/04
摘要： An aspect includes coherency management between volatile memory and non-volatile memory in a through-silicon via (TSV) module of a computer system. A plurality of TSV write signals is simultaneously provided to the volatile memory and the non-volatile memory. A plurality of values of the TSV write signals is captured within a buffer of the non-volatile memory corresponding to a data set written to the volatile memory. Storage space is freed within the buffer as the data set corresponding to the values of the TSV write signals stored within the buffer is written to a non-volatile memory array within the non-volatile memory.
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公开(公告)号：US20180018217A1
公开(公告)日：2018-01-18
申请号：US15207679
申请日：2016-07-12
CPC分类号： G06F11/1004 , G06F11/10
摘要： An aspect includes a method for auto-disabling dynamic random access memory (DRAM) error checking based on a threshold. A method includes receiving data at a DRAM from a memory controller and executing error checking logic based on the data. The error checking logic detects and error condition in the data and it is determined, at the DRAM, whether detecting the error condition in the data causes an error threshold to be reached. The error checking logic is disabled at the DRAM in response to determining that detecting the error condition in the data causes the error the error threshold to be reached. The error condition is communicated to the memory controller in response to determining that detecting the error condition does not cause the error threshold to be reached.
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24.发明申请公开(公告)号：US20170308309A1
公开(公告)日：2017-10-26
申请号：US15138629
申请日：2016-04-26
IPC分类号： G06F3/06 , G11C11/4096 , G11C11/406 , G06F11/20 , G11C14/00
CPC分类号： G06F3/0619 , G06F3/0608 , G06F3/065 , G06F3/0652 , G06F3/0656 , G06F3/0659 , G06F3/0685 , G06F11/2015 , G06F2201/805 , G06F2201/86 , G11C5/04 , G11C14/0018
摘要： An aspect includes coherency management between volatile memory and non-volatile memory in a through-silicon via (TSV) module of a computer system. A plurality of TSV write signals is simultaneously provided to the volatile memory and the non-volatile memory. A plurality of values of the TSV write signals is captured within a buffer of the non-volatile memory corresponding to a data set written to the volatile memory. Storage space is freed within the buffer as the data set corresponding to the values of the TSV write signals stored within the buffer is written to a non-volatile memory array within the non-volatile memory.
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公开(公告)号：US09230687B2
公开(公告)日：2016-01-05
申请号：US13867207
申请日：2013-04-22
发明人： Edgar R. Cordero , Timothy J. Dell , Joab D. Henderson , Jeffrey A. Sabrowski , Anuwat Saetow , Saravanan Sethuraman
CPC分类号： G11C29/4401 , G06F11/1048 , G11C29/42 , G11C29/702 , G11C2029/0411 , G11C2029/4402
摘要： A method, system and computer program product are provided for implementing ECC (Error Correction Codes) redundancy using reconfigurable logic blocks in a computer system. When a fail is detected when reading from memory, it is determined if the incorrect data is in the data or the ECC component of the data. When incorrect data is found in the ECC component of the data, and an actionable threshold is not reached, a predetermined Reliability, Availability, and Serviceability (RAS) action is taken. When the actionable threshold is reached with incorrect data identified in the ECC component of the data, an analysis process is performed to determine if the ECC logic is faulty. When a fail in the ECC logic is detected, the identified ECC failed logic is replaced with a spare block of logic.
摘要翻译： 提供了一种方法，系统和计算机程序产品，用于在计算机系统中使用可重新配置的逻辑块实现ECC（纠错码）冗余。 当从存储器读取时检测到故障时，确定数据中的错误数据是否在数据或ECC组件中。 当在数据的ECC组件中找到不正确的数据，并且没有达到可操作的阈值时，采取预定的可靠性，可用性和可服务性（RAS）动作。 当在数据的ECC组件中识别出不正确的数据达到可操作的阈值时，执行分析处理以确定ECC逻辑是否有故障。 当检测到ECC逻辑中的故障时，所识别的ECC故障逻辑被替换为备用逻辑块。
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26.发明申请IMPLEMENTING SIMULTANEOUS READ AND WRITE OPERATIONS UTILIZING DUAL PORT DRAM 有权实现同时使用双端口DRAM的读取和写入操作公开(公告)号：US20150213854A1
公开(公告)日：2015-07-30
申请号：US14310717
申请日：2014-06-20
发明人： Edgar R. Cordero , Carlos A. Fernandez , Joab D. Henderson , Jeffrey A. Sabrowski , Anuwat Saetow , Saravanan Sethuraman
IPC分类号： G11C7/10
CPC分类号： G11C7/1075 , G06F11/1048 , G11C7/1045 , G11C8/16 , G11C2029/0411 , G11C2207/2209
摘要： A method, system and memory controller are provided for implementing simultaneous read and write operations in a memory subsystem utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. A DRAM includes a first partition and a second partition. A memory controller determines if memory requirements are above or below a usage threshold. If the memory requirements are below the usage threshold, the memory is partitioned into a read buffer and a write buffer, with writes going to the write buffer and reads coming from the read buffer, data being transferred from the write buffer to the read buffer through an Error Correction Code (ECC) engine. If the memory requirements are above the usage threshold, the entire memory is used for reads and writes.
摘要翻译： 提供了一种方法，系统和存储器控制器，用于在利用双端口动态随机存取存储器（DRAM）配置的存储器子系统中实现同时的读和写操作。 DRAM包括第一分区和第二分区。 存储器控制器确定存储器需求是否高于或低于使用阈值。 如果存储器要求低于使用阈值，则存储器被划分为读缓冲器和写缓冲器，其中写入缓冲器的写入和来自读缓冲器的读取，数据从写缓冲器传送到读缓冲器，通过 纠错码（ECC）引擎。 如果内存要求高于使用阈值，则整个内存将用于读取和写入。
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公开(公告)号：US20140250340A1
公开(公告)日：2014-09-04
申请号：US13781807
申请日：2013-03-01
发明人： Edgar R. Cordero , Timothy J. Dell , Joab D. Henderson , Jeffrey A. Sabrowski , Anuwat Saetow , Saravanan Sethuraman
IPC分类号： G06F11/28
CPC分类号： G06F11/10 , G06F11/1048 , G06F11/2017 , G06F11/28 , H03M13/29
摘要： Exemplary embodiments of the present invention disclose a method and system for monitoring a first Error Correcting Code (ECC) device for failure and replacing the first ECC device with a second ECC device if the first ECC device begins to fail or fails. In a step, an exemplary embodiment detects that a specified number of correctable errors is exceeded. In another step, an exemplary embodiment detects the occurrence of an uncorrectable error. In another step, an exemplary embodiment performs a loopback test on an ECC device if a specified number of correctable errors is exceeded or if an uncorrectable error occurs. In another step, an exemplary embodiment replaces an ECC device that fails the loopback test with an ECC device that passes a loopback test.
摘要翻译： 本发明的示例性实施例公开了一种用于监视第一纠错码（ECC）设备的方法和系统，用于如果第一ECC设备开始失败或失败，则用第二ECC设备故障并替换第一ECC设备。 在一个步骤中，示例性实施例检测到超过了指定数量的可校正错误。 在另一步骤中，示例性实施例检测出不可校正的错误。 在另一步骤中，如果超过指定数量的可校正错误或者发生不可校正的错误，则示例性实施例对ECC设备执行环回测试。 在另一步骤中，示例性实施例用通过环回测试的ECC设备替代了对环回测试失败的ECC设备。
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公开(公告)号：US20230153190A1
公开(公告)日：2023-05-18
申请号：US17454987
申请日：2021-11-15
CPC分类号： G06F11/0772 , G06F11/0787 , G06F11/079 , G06F11/0793 , G06F11/3664
摘要： In an approach to improve resolving defects within computer hardware, programs, software, or systems, embodiments pause mainline traffic and isolating interface or retention issues, and determine one or more types of errors in an event of a mainline traffic fail, wherein debug techniques are applied to fail information to resolve or further diagnose the one or more types of errors, and wherein the debug techniques are tracked and categorized. Additionally, embodiments apply corrective read actions to a detected error based on previously stored corrective actions associated with the detected error, and responsive to identifying no additional actions are required, restoring a collected system data. Further, embodiments, resume the paused mainline traffic.
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公开(公告)号：US10936222B2
公开(公告)日：2021-03-02
申请号：US16445485
申请日：2019-06-19
发明人： Anuwat Saetow , Stephen Glancy
摘要： A computer-implemented method for calibrating DRAM is provided. A non-limiting example of the computer-implemented method includes reading, by a processor, system configuration information and disabling, by the processor, one or more steps in a list of calibration steps to be performed based on the system configuration information to leave a list of remaining calibration steps. Based on a determination that two or more remaining calibration steps are co-dependent, the method configures, by the processor, a single calibration step that encapsulates the co-dependent algorithm and places, by the processor, the single calibration step in a list of steps to be called. The method then provides, by the processor, the list of steps to be called.
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公开(公告)号：US10324879B2
公开(公告)日：2019-06-18
申请号：US15278665
申请日：2016-09-28
发明人： David D. Cadigan , Samuel R. Connor , Michael A. Cracraft , William V. Huott , Adam J. McPadden , Anuwat Saetow , Gary A. Tressler
IPC分类号： G06F13/40 , G06F13/42 , G06F1/3296
摘要： An apparatus and method may detect and reduce noise on data busses by adjusting the phase of the input/output (I/O) signals in a controlled, predictable manner. The control may allow a maximum data rate to be achieved. In one embodiment, an algorithm used to determine phase change data may be handled by a feedback loop and may be dynamically adjusted. The system may detect noise on rails and critical signals for logging in call home data. The system may maintain a database of settings as a function of a workload. The system may be used in the field as the workload changes to determine that a signal has reached a first threshold. In response to determining that the signal has reached the first threshold, an alert is initiated. A system may determine that the signal has reached a second threshold. In response to determining that the signal has reached the second threshold, the signal may be coupled to logic circuitry.
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