公开(公告)号：US10256326B2

公开(公告)日：2019-04-09

申请号：US15368089

申请日：2016-12-02

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Fee Li Lie ,  Eric R. Miller ,  Jeffrey C. Shearer ,  John R. Sporre ,  Sean Teehan

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/306 ,  H01L29/16 ,  H01L29/78 ,  H01L29/40 ,  H01L29/775

Abstract: A semiconductor device comprises a nanowire arranged over a substrate, a gate stack arranged around the nanowire, a spacer arranged along a sidewall of the gate stack, a cavity defined by a distal end of the nanowire and the spacer, and a source/drain region partially disposed in the cavity and in contact with the distal end of the nanowire.

公开(公告)号：US10243079B2

公开(公告)日：2019-03-26

申请号：US15639721

申请日：2017-06-30

Applicant: International Business Machines Corporation

Inventor： Andrew M. Greene ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Eric R. Miller ,  Pietro Montanini

IPC: H01L29/78 ,  H01L29/66

Abstract: FinFET devices comprising multilayer gate spacers are provided, as well as methods for fabricating FinFET devices in which multilayer gate spacers are utilized to prevent or otherwise minimize the erosion of vertical semiconductor fins when forming the gate spacers. For example, a method for fabricating a semiconductor device comprises forming a dummy gate structure over a portion of a vertical semiconductor fin of a FinFET device, and forming a multilayer gate spacer on the dummy gate structure. The multilayer gate spacer comprises a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has etch selectivity with respect to the vertical semiconductor fin and the second dielectric layer. In one embodiment, the first dielectric layer comprises silicon oxycarbonitride (SiOCN) and the second dielectric layer comprises silicon boron carbon nitride (SiBCN).

公开(公告)号：US20180350812A1

公开(公告)日：2018-12-06

申请号：US16040033

申请日：2018-07-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Fee Li Lie ,  Eric R. Miller ,  Sean Teehan

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/161 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L27/0922 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a complementary metal oxide semiconductor (CMOS) device on a substrate, including forming a plurality of vertical fins on the substrate, forming a first set of source/drain projections on the first subset of vertical fins, forming a second set of source/drain projections on the second subset of vertical fins, where the second set of source/drain projections is a different oxidizable material from the oxidizable material of the first set of source/drain projections, converting a portion of each of the second set of source/drain projections and a portion of each of the first set of source/drain projections to an oxide, removing the converted oxide portion of the first set of source/drain projections to form a source/drain seed mandrel, and removing a portion of the converted oxide portion of the second set of source/drain projections to form a dummy post.

公开(公告)号：US10014391B2

公开(公告)日：2018-07-03

申请号：US15195332

申请日：2016-06-28

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Fee Li Lie ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/308

CPC classification number: H01L29/6656 ,  H01L21/3083 ,  H01L21/3085 ,  H01L29/0649 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/785

Abstract: Techniques relate to a gate stack for a semiconductor device. A vertical fin is formed on a substrate. The vertical fin has an upper portion and a bottom portion. The upper portion of the vertical fin has a recessed portion on sides of the upper portion. A gate stack is formed in the recessed portion of the upper portion of the vertical fin.

公开(公告)号：US09997369B2

公开(公告)日：2018-06-12

申请号：US15277431

申请日：2016-09-27

Applicant: International Business Machines Corporation

Inventor： Gauri Karve ,  Fee Li Lie ,  Eric R. Miller ,  Stuart A. Sieg ,  John R. Sporre ,  Sean Teehan

IPC: H01L29/78 ,  H01L21/308 ,  H01L21/311

CPC classification number: H01L21/3086 ,  H01L21/0337

Abstract: A method for fabricating a semiconductor structure. The method includes forming a plurality of mandrel structures. A plurality of first spacers is formed on sidewalls of the mandrel structures. A plurality of second spacers is formed on sidewalls of the first spacers. The plurality of first spacers is removed selective to the plurality of second spacers and mandrel structures. A cut mask is formed over a first set of second spacers in the plurality of second spacers and a first set of mandrel structures in the plurality of mandrel structures. A second set of second spacers in the plurality of spacers and a second set of mandrel structures in the plurality of mandrel structures remain exposed. One of the second set of mandrel structures and the second set of second spacers is removed selective to the second set of second spacers and the second set of mandrel structures, respectively.

公开(公告)号：US20180076225A1

公开(公告)日：2018-03-15

申请号：US15263005

申请日：2016-09-12

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Gauri Karve ,  Fee Li Lie ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/306 ,  H01L21/308 ,  H01L21/762 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L21/84

CPC classification number: H01L27/1207 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Sub-fin removal techniques for SOI like isolation in finFET devices are provided. In one aspect, a method for forming a finFET device includes: etching partial fins in a substrate, wherein the partial fins include top portions of fins of the finFET device; forming a bi-layer spacer on the top portions of the fins; complete etching of the fins in the substrate to form bottom portions of the fins of the finFET device; depositing an insulator between the fins; recessing the insulator enough to expose a region of the fins not covered by the bi-layer spacer; removing the exposed region of the fins to create a gap between the top and bottom portions of the fins; filling the gap with additional insulator. A method for forming a finFET device is also provided where placement of the fin spacer occurs after (rather than before) insulator deposition. A finFET device is also provided.

公开(公告)号：US09905643B1

公开(公告)日：2018-02-27

申请号：US15248237

申请日：2016-08-26

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC: H01L29/66 ,  H01L29/161 ,  H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/786

CPC classification number: H01L29/78618 ,  B82Y10/00 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696 ,  H05K999/99

Abstract: A nano-sheet semiconductor structure and a method for fabricating the same. The nano-sheet structure includes a substrate and at least one alternating stack of semiconductor material layers and metal gate material layers. The nano-sheet semiconductor structure further comprises a source region and a drain region. A first plurality of epitaxially grown interconnects contacts the source region and the semiconductor layers in the alternating stack. A second plurality of epitaxially grown interconnects contacts the drain region and the semiconductor layers in the alternating stack. The method includes removing a portion of alternating semiconductor layers and metal gate material layers. A first plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the source region. A second plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the drain region.

公开(公告)号：US09754942B2

公开(公告)日：2017-09-05

申请号：US15170333

申请日：2016-06-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Jessica Dechene ,  Fee Li Lie ,  Eric R. Miller ,  Jeffrey C. Shearer ,  John R. Sporre ,  Sean Teehan

IPC: H01L21/66 ,  H01L27/092 ,  H01L29/161 ,  H01L29/167

CPC classification number: H01L27/0924 ,  H01L21/02236 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/7848

Abstract: A method of forming a semiconductor device that includes forming a high-k dielectric fin liner on the first plurality of fin structures in a first device region and a second plurality of fin structures in a second device region, and forming a gate structure including a low-k dielectric gate sidewall spacer on the channel region of the first and second plurality of fin structures. A first epitaxial semiconductor material on the first plurality of fin structures from which the high-k dielectric fin liner has been removed. The first epitaxial semiconductor material is then oxidized, and a remaining portion of the high-k dielectric fin liner is removed. A second epitaxial semiconductor material is formed on the second plurality of fin structures.

公开(公告)号：US09748146B1

公开(公告)日：2017-08-29

申请号：US15240578

申请日：2016-08-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Jessica Dechene ,  Fee Li Lie ,  Eric R. Miller ,  Jeffrey C. Shearer ,  John R. Sporre ,  Sean Teehan

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/02

CPC classification number: H01L27/0924 ,  H01L21/02236 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/7848

Abstract: A method of forming a semiconductor device that includes forming a high-k dielectric fin liner on the first plurality of fin structures in a first device region and a second plurality of fin structures in a second device region, and forming a gate structure including a low-k dielectric gate sidewall spacer on the channel region of the first and second plurality of fin structures. A first epitaxial semiconductor material on the first plurality of fin structures from which the high-k dielectric fin liner has been removed. The first epitaxial semiconductor material is then oxidized, and a remaining portion of the high-k dielectric fin liner is removed. A second epitaxial semiconductor material is formed on the second plurality of fin structures.

公开(公告)号：US09716184B2

公开(公告)日：2017-07-25

申请号：US15158033

申请日：2016-05-18

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Sivananda K. Kanakasabapathy ,  Fee Li Lie ,  Eric R. Miller ,  Jeffrey C. Shearer ,  John R. Sporre ,  Sean Teehan

IPC: H01L29/792 ,  H01L23/544 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L29/792 ,  H01L21/0337 ,  H01L21/28282 ,  H01L21/31144 ,  H01L23/544 ,  H01L29/4916 ,  H01L29/66833 ,  H01L2223/54426 ,  H01L2223/54453

Abstract: In an embodiment, this disclosure relates to a method of creating an alignment feature within a sidewall image transfer process by the addition of a block mask. The presence of the alignment feature would enable better overlay and alignment for subsequent lithographic stacks.