公开(公告)号：US20190115392A1

公开(公告)日：2019-04-18

申请号：US15784343

申请日：2017-10-16

Applicant: International Business Machines Corporation

Inventor： ROBERT BRUCE ,  Fabio Carta ,  Gloria WingYun Fraczak ,  Hiroyuki Miyazoe ,  Kumar R. Virwani

IPC: H01L27/24 ,  H01L45/00

Abstract: A combined semiconductor device is fabricated by forming a first access structure from a mixed ionic electronic conduction (MIEC) material. A first side of a first memory structure is electrically coupled with a first side of the first access structure to form the combination device. A subtractive etching process is applied to the combination device such that a surface of the combination device that is substantially orthogonal to a plane of a substrate of the semiconductor device is within a defined tapering tolerance.

公开(公告)号：US10256271B1

公开(公告)日：2019-04-09

申请号：US15827238

申请日：2017-11-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bahman Hekmatshoartabari ,  Chung H. Lam ,  Fabio Carta ,  Matthew J. BrightSky

IPC: H01L27/24 ,  H01L21/02 ,  H01L45/00 ,  G11C13/00

Abstract: A method for deactivating memory cells affected by the presence of grain boundaries in polycrystalline selection devices includes crystallizing a semiconductor layer in a diode stack to form a polycrystalline layer for selection diodes formed in a crossbar array. To achieve a crystalline state in phase change memory elements coupled to corresponding selection diodes perform an anneal. Memory cells having shunted selection diodes due to grain boundaries are identified by scanning the array using sense voltages. A second voltage larger than the sense voltages is applied to the phase change memory elements gated by the shunted selection diodes such that the phase change memory elements gated by the shunted diodes achieve a permanently high resistive state.

公开(公告)号：US09425298B2

公开(公告)日：2016-08-23

申请号：US14602799

申请日：2015-01-22

Applicant: International Business Machines Corporation

Inventor： Fabio Carta ,  Daniel C. Edelstein ,  Stephen M. Gates ,  Bahman Hekmatshoartabari ,  Tak H. Ning

IPC: H01L23/48 ,  H01L29/735 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/06 ,  H01L23/29 ,  H01L23/31 ,  H01L21/311 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/225

CPC classification number: H01L29/6625 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/2251 ,  H01L21/2254 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/32105 ,  H01L21/324 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/42304 ,  H01L29/735 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A bipolar junction transistor comprises a semiconductor layer disposed on an insulating material, at least a portion of the semiconductor layer forming a base region. The bipolar junction transistor further comprises a transistor emitter laterally disposed on a first side of the base region, where in the transistor emitter is a first doping type and has a first width, and wherein the first width is a lithographic feature size. The bipolar junction transistor further comprises a transistor collector laterally disposed on a second side of the base region, wherein the transistor collector is the first doping type and the first width. The bipolar junction transistor further comprises a central base contact laterally disposed on the base region between the transistor emitter and the transistor collector, wherein the central base contact is a second doping type and has a second width, and wherein the second width is a sub-lithographic feature size.

Abstract translation: 双极结型晶体管包括设置在绝缘材料上的半导体层，半导体层的至少一部分形成基极区域。 所述双极结晶体管还包括横向设置在所述基极区域的第一侧上的晶体管发射极，其中所述晶体管发射极是第一掺杂型并具有第一宽度，并且其中所述第一宽度是光刻特征尺寸。 双极结晶体管还包括横向设置在基极区的第二侧上的晶体管集电极，其中晶体管集电极是第一掺杂型和第一宽度。 双极结晶体管还包括横向设置在晶体管发射极和晶体管集电极之间的基极区上的中心基极接触，其中中心基极接触是第二掺杂型并具有第二宽度，并且其中第二宽度是亚晶体， 光刻特征尺寸。

公开(公告)号：US20230189670A1

公开(公告)日：2023-06-15

申请号：US17546178

申请日：2021-12-09

Applicant: International Business Machines Corporation

Inventor： Fabio Carta ,  Chung Hon Lam ,  Wanki Kim ,  Robert L. Bruce

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1253 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/144 ,  H01L45/1608

Abstract: A memory cell with a recessed bottom electrode and methods of forming the memory cell are described. A bottom electrode can be deposited on a layer of a structure. A first insulator and a second insulator can be deposited on top of the bottom electrode. The first insulator and the second insulator can be spaced apart from one another to form an opening on top of the bottom electrode. A recess can be etched in the bottom electrode. The recess can be etched in a portion of the bottom electrode that is underneath the opening. The recess and the opening can form a pore. Phase change material can be deposited in the pore to form a memory cell.

公开(公告)号：US11562931B2

公开(公告)日：2023-01-24

申请号：US17350014

申请日：2021-06-17

Applicant: International Business Machines Corporation

Inventor： Fabio Carta ,  Matthew Joseph BrightSky

IPC: H01L21/8234 ,  H01L27/24 ,  H01L21/02 ,  H01L29/786 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423

Abstract: A method of manufacturing a vertical metal-semiconductor field-effect transistor (MESFET) device is provided. The method includes forming a first oxide layer, forming a first electrode in the oxide layer, forming a crystallized silicon layer on the first electrode, forming a second electrode on the first oxide layer and on sidewalls of the crystalized silicon layer, forming a second oxide layer on upper surfaces of the second electrode. The method also includes forming a third electrode on an upper surface of the crystallized silicon layer.

公开(公告)号：US20220406843A1

公开(公告)日：2022-12-22

申请号：US17350014

申请日：2021-06-17

Applicant: International Business Machines Corporation

Inventor： Fabio Carta ,  Matthew Joseph BrightSky

IPC: H01L27/24 ,  H01L21/02 ,  H01L29/66 ,  H01L29/786

Abstract: A method of manufacturing a vertical metal-semiconductor field-effect transistor (MESFET) device is provided. The method includes forming a first oxide layer, forming a first electrode in the oxide layer, forming a crystallized silicon layer on the first electrode, forming a second electrode on the first oxide layer and on sidewalls of the crystalized silicon layer, forming a second oxide layer on upper surfaces of the second electrode. The method also includes forming a third electrode on an upper surface of the crystallized silicon layer.

公开(公告)号：US20220367797A1

公开(公告)日：2022-11-17

申请号：US17876237

申请日：2022-07-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Wanki Kim ,  Fabio Carta ,  Chung H. Lam ,  Robert L. Bruce

IPC: H01L45/00 ,  H01L27/24

Abstract: A method for fabricating a semiconductor device includes forming air gaps within respective dielectric layer portions to reduce thermal cross-talk between adjacent bits. Each of the dielectric portions is formed on a substrate each adjacent to sidewall liners formed on sidewalls of a phase change memory (PCM) layer. The method further includes forming a pillar including the sidewall liners and the PCM layer, and forming a selector layer on the pillar and the dielectric portions.

公开(公告)号：US10930705B2

公开(公告)日：2021-02-23

申请号：US15938625

申请日：2018-03-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Fabio Carta ,  Chung H. Lam ,  Matthew J. BrightSky ,  Bahman Hekmatshoartabari

IPC: H01L27/24 ,  H01L45/00 ,  H01L21/02 ,  H01L29/16 ,  H01L29/861 ,  H01L29/868 ,  H01L29/66 ,  H01L29/04

Abstract: A method is presented for integrating an electronic component in back end of the line (BEOL) processing. The method includes forming a first electrode over a semiconductor substrate, forming a first electrically conductive material over a portion of the first electrode, forming a second electrically conductive material over the first electrically conductive material, where the first and second electrically conductive materials define a p-n junction, depositing a phase change material over the p-n junction, and forming a second electrode over the phase change material.

公开(公告)号：US20210050384A1

公开(公告)日：2021-02-18

申请号：US16542929

申请日：2019-08-16

Applicant: International Business Machines Corporation

Inventor： Fabio Carta ,  Matthew J. BrightSky ,  Bahman Hekmatshoartabari ,  Asit Ray ,  Wanki Kim

IPC: H01L27/24 ,  H01L45/00 ,  H01L29/04 ,  H01L29/16 ,  H01L29/861 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3213

Abstract: A method of fabricating an access device in a crosspoint memory array structure during BEOL processing includes: forming at least a first doped semiconductor layer on an upper surface of a first conductive layer, the first doped semiconductor layer being in electrical connection with the first conductive layer; exposing at least a portion of the first doped semiconductor layer to a directed energy source to cause localized annealing in the first doped semiconductor layer to activate a dopant of a first conductivity type in the first doped semiconductor layer, thereby converting at least a portion of the first doped semiconductor layer into a polycrystalline layer; forming a second conductive layer over a least a portion of the first doped semiconductor layer; and etching the first doped semiconductor layer and the first and second conductive layers to form an access device that is self-aligned with the first and second conductive layers.

公开(公告)号：US10892413B2

公开(公告)日：2021-01-12

申请号：US15408392

申请日：2017-01-17

Applicant: International Business Machines Corporation

Inventor： Robert L. Bruce ,  Fabio Carta ,  Wanki Kim ,  Chung H. Lam

IPC: H01L45/00 ,  H01L27/24

Abstract: A phase change memory array and method for fabricating the same. The phase change memory array includes a plurality of bottom electrodes, top electrodes, and memory pillars. Each of the memory pillars includes phase change material surrounded by a dielectric casing. The phase change material is positioned between, and in series circuit with, a respective bottom electrode from the bottom electrodes and a respective top electrode from the top electrodes. A continuous layer of selector material is positioned between the memory pillars and the plurality of bottom electrodes. The selector material is configured to conduct electricity only when a voltage across the selector material exceeds a voltage threshold.