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    BURIED SOURCE-DRAIN CONTACT FOR INTEGRATED CIRCUIT TRANSISTOR DEVICES AND METHOD OF MAKING SAME
    22.
    发明申请
    BURIED SOURCE-DRAIN CONTACT FOR INTEGRATED CIRCUIT TRANSISTOR DEVICES AND METHOD OF MAKING SAME 有权
    用于集成电路晶体管器件的引出源漏极触点及其制造方法

    公开(公告)号：US20150357425A1

    公开(公告)日：2015-12-10

    申请号：US14297822

    申请日：2014-06-06

    Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh ,  Xiuyu Cai ,  William J. Taylor

    IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78

    CPC classification number: H01L21/823475 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

    Abstract: An integrated circuit transistor is formed on a substrate. A trench in the substrate is at least partially filed with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region in the substrate which is in electrical connection with the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate may be of the silicon on insulator (SOI) or bulk type. The buried source (or drain) contact makes electrical connection to a side of the source (or drain) region using a junction provided at a same level of the substrate as the source (or drain) and channel regions.

    Abstract translation: 在基板上形成集成电路晶体管。 衬底中的沟槽至少部分地与金属材料填充以形成埋在衬底中的源极（或漏极）接触。 衬底还包括与源极（或漏极）接触电连接的衬底中的源极（或漏极）区域。 衬底还包括与源极（或漏极）区域相邻的沟道区域。 栅极电介质设置在沟道区域的顶部，栅电极设置在栅极电介质的顶部。 衬底可以是绝缘体上硅（SOI）或体积型。 埋入的源极（或漏极）接触器使用与源极（或漏极）和沟道区域在基底的相同水平处提供的接点，使得与源极（或漏极）区域的一侧电连接。

    FinFETs and techniques for controlling source and drain junction profiles in finFETs
    23.
    发明授权
    FinFETs and techniques for controlling source and drain junction profiles in finFETs 有权
    FinFET和用于控制finFET中的源极和漏极结型材的技术

    公开(公告)号：US09202919B1

    公开(公告)日：2015-12-01

    申请号：US14447685

    申请日：2014-07-31

    Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

    Inventor： Qing Liu ,  Ruilong Xie ,  Xiuyu Cai ,  Kejia Wang ,  Chun-chen Yeh

    IPC: H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848

    Abstract: Techniques and structures for shaping the source and drain junction profiles of a finFET are described. A fin may be partially recessed at the source and drain regions of the finFET. The partially recessed fin may be further recessed laterally and vertically, such that the laterally recessed portion extends under at least a portion of the finFET's gate structure. Source and drain regions of the finFET may be formed by growing a buffer layer on the etched surfaces of the fin and/or growing a source and drain layer at the source and drain regions of the fin. The lateral recess can improve channel-length uniformity along the height of the fin.

    Abstract translation: 描述了用于成形finFET的源极和漏极结线廓的技术和结构。 翅片可以部分地凹陷在finFET的源极和漏极区域。 部分凹入的翅片可以进一步侧向和垂直地凹入，使得横向凹入部分在finFET的栅极结构的至少一部分下方延伸。 可以通过在鳍的蚀刻表面上生长缓冲层和/或在鳍的源极和漏极区生长源极和漏极层来形成鳍FET的源区和漏极区。 横向凹槽可以改善沿翅片高度的通道长度均匀性。

    METHOD FOR THE FORMATION OF FIN STRUCTURES FOR FINFET DEVICES
    25.
    发明申请
    METHOD FOR THE FORMATION OF FIN STRUCTURES FOR FINFET DEVICES 审中-公开
    用于形成FINFET器件的FIN结构的方法

    公开(公告)号：US20140353767A1

    公开(公告)日：2014-12-04

    申请号：US13906505

    申请日：2013-05-31

    Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

    Inventor： Qing Liu ,  Nicolas Loubet ,  Shom Ponoth ,  Prasanna Khare ,  Balasubramanian Pranatharthiharan

    IPC: H01L27/092 ,  H01L21/8238

    CPC classification number: H01L21/845 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/76224 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/1211 ,  H01L29/6653 ,  H01L29/6656

    Abstract: On a first semiconductor material substrate, an overlying sacrificial layer formed of a second semiconductor material is deposited. In a first region, a first semiconductor material region is formed over the sacrificial layer. In a second region, a second semiconductor material region is formed over the sacrificial layer. The first semiconductor material region is patterned to define a first FinFET fin. The second semiconductor material region is patterned to define a second FinFET fin. The fins are each covered with a cap and sidewall spacer. The sacrificial layer formed of the second semiconductor material is then selectively removed to form an opening below each of the first and second FinFET fins (with those fins being supported by the sidewall spacers). The openings below each of the fins are then filled with a dielectric material that serves to isolate the semiconductive materials of the fins from the substrate.

    Abstract translation: 在第一半导体材料基板上沉积由第二半导体材料形成的上覆牺牲层。 在第一区域中，在牺牲层上形成第一半导体材料区域。 在第二区域中，在牺牲层上形成第二半导体材料区域。 图案化第一半导体材料区域以限定第一FinFET鳍片。 图案化第二半导体材料区域以限定第二FinFET鳍片。 翅片各自被盖和侧壁间隔物覆盖。 然后选择性地去除由第二半导体材料形成的牺牲层，以在第一和第二FinFET鳍片下面形成开口（这些鳍片由侧壁间隔件支撑）。 然后每个翅片下面的开口填充有用于将鳍片的半导体材料与衬底隔离的介电材料。

    Memory device having multiple dielectric gate stacks with first and second dielectric layers and related methods
    27.
    发明授权
    Memory device having multiple dielectric gate stacks with first and second dielectric layers and related methods 有权
    具有具有第一和第二介电层的多个介电栅极堆叠的存储器件和相关方法

    公开(公告)号：US08860123B1

    公开(公告)日：2014-10-14

    申请号：US13852720

    申请日：2013-03-28

    Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

    Inventor： Prasanna Khare ,  Stephane Allegret-Maret ,  Nicolas Loubet ,  Qing Liu ,  Hemanth Jagannathan ,  Lisa Edge ,  Kangguo Cheng ,  Bruce Doris

    IPC: H01L29/792 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66

    CPC classification number: H01L29/792 ,  H01L21/28273 ,  H01L27/11546 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

    Abstract: A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack having a first dielectric layer over the channel region, a second dielectric layer over the first dielectric layer, a first diffusion barrier layer over the second dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second diffusion barrier layer over the first electrically conductive layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer.

    Abstract translation: 存储器件可以包括半导体衬底和半导体衬底中的存储晶体管。 存储晶体管可以包括半导体衬底中的源极和漏极区域以及它们之间的沟道区域，以及栅极堆叠，其在沟道区域上具有第一介电层，在第一介电层上方具有第二介电层，第一扩散阻挡层 第一介电层，第一扩散阻挡层上的第一导电层，第一导电层上的第二扩散阻挡层，以及第二扩散阻挡层上的第二导电层。 第一和第二电介质层可以包括不同的电介质材料，并且第一扩散阻挡层可以比第二扩散阻挡层薄。

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