公开(公告)号：US09059196B2

公开(公告)日：2015-06-16

申请号：US14070989

申请日：2013-11-04

Applicant: International Business Machines Corporation

Inventor： John J. Benoit ,  James R. Elliot ,  Peter B. Gray ,  Alvin J. Joseph ,  Qizhi Liu ,  Christa R. Willets

IPC: H01L21/762 ,  H01L29/73 ,  H01L29/66 ,  H01L29/732

CPC classification number: H01L29/732 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/66272 ,  H01L29/7371 ,  H01L29/7378

Abstract: Device structures, design structures, and fabrication methods for a bipolar junction transistor. A first layer comprised of a first semiconductor material and a second layer comprised of a second semiconductor material are disposed on a substrate containing a first terminal of the bipolar junction transistor. The second layer is disposed on the first layer and a patterned etch mask is formed on the second layer. A trench extends through the pattern hardmask layer, the first layer, and the second layer and into the substrate. The trench defines a section of the first layer stacked with a section of the second layer. A selective etching process is used to narrow the section of the second layer relative to the section of the first layer to define a second terminal and to widen a portion of the trench in the substrate to undercut the section of the first layer.

Abstract translation: 双极结型晶体管的器件结构，设计结构和制造方法。 由包含第一半导体材料的第一层和由第二半导体材料组成的第二层设置在包含双极结型晶体管的第一端子的衬底上。 第二层设置在第一层上，并且在第二层上形成图案化的蚀刻掩模。 沟槽延伸穿过图案硬掩模层，第一层和第二层并进入衬底。 沟槽限定了与第二层的一部分堆叠的第一层的一部分。 使用选择性蚀刻工艺来相对于第一层的截面来缩小第二层的截面以限定第二端子并且加宽衬底中的沟槽的一部分以削弱第一层的部分。

公开(公告)号：US09029949B2

公开(公告)日：2015-05-12

申请号：US14036158

申请日：2013-09-25

Applicant: International Business Machines Corporation

Inventor： Jeffrey P. Gambino ,  Qizhi Liu ,  Zhenzhen Ye ,  Yan Zhang

IPC: H01L27/12 ,  H01L21/00 ,  H01L23/34 ,  H01L21/283

CPC classification number: H01L23/34 ,  H01L21/283 ,  H01L21/76264 ,  H01L21/84 ,  H01L23/367 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78606 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed are semiconductor-on-insulator (SOI) structures comprising an SOI device (e.g., an SOI metal oxide semiconductor field effect transistor (MOSFET)) with local heat dissipater(s). Each heat dissipater comprises an opening, which is adjacent an active region of the SOI device, which extends through the insulator layer on which the SOI device sits to the semiconductor substrate below, and which is at least partially filled with a fill material. This fill material is a thermal conductor so as to dissipate heat generated by the SOI device and is also an electrical isolator so as to minimize current leakage. In the case of MOSFET, the local heat dissipater(s) can be aligned below the source/drain extension(s) or the source/drain(s). Alternatively, the local heat dissipater(s) can be aligned below the channel or parallel and adjacent to opposing sides of the channel. Also disclosed herein are methods of forming these SOI structures.

Abstract translation: 公开了包括具有局部散热器的SOI器件（例如，SOI金属氧化物半导体场效应晶体管（MOSFET））的绝缘体上半导体（SOI）结构。 每个散热器包括与SOI器件的有源区相邻的开口，该开口延伸穿过SOI器件位于半导体衬底下面的绝缘体层，并且至少部分地填充有填充材料。 该填充材料是导热体，以散发由SOI器件产生的热量，并且也是电隔离器，以便最小化电流泄漏。 在MOSFET的情况下，局部散热器可以在源极/漏极延伸部分或源极/漏极之下对准。 或者，局部散热器可以在通道下方对准或平行并邻近通道的相对侧。 本文还公开了形成这些SOI结构的方法。

公开(公告)号：US20150123245A1

公开(公告)日：2015-05-07

申请号：US14070989

申请日：2013-11-04

Applicant: International Business Machines Corporation

Inventor： John J. Benoit ,  James R. Elliott ,  Peter B. Gray ,  Alvin J. Joseph ,  Qizhi Liu ,  Christa R. Willets

IPC: H01L29/66 ,  H01L29/732

CPC classification number: H01L29/732 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/66272 ,  H01L29/7371 ,  H01L29/7378

Abstract: Device structures, design structures, and fabrication methods for a bipolar junction transistor. A first layer comprised of a first semiconductor material and a second layer comprised of a second semiconductor material are disposed on a substrate containing a first terminal of the bipolar junction transistor. The second layer is disposed on the first layer and a patterned etch mask is formed on the second layer. A trench extends through the pattern hardmask layer, the first layer, and the second layer and into the substrate. The trench defines a section of the first layer stacked with a section of the second layer. A selective etching process is used to narrow the section of the second layer relative to the section of the first layer to define a second terminal and to widen a portion of the trench in the substrate to undercut the section of the first layer.

公开(公告)号：US20150054123A1

公开(公告)日：2015-02-26

申请号：US14522090

申请日：2014-10-23

Applicant: International Business Machines Corporation

Inventor： Margaret A. Faucher ,  Paula M. Fisher ,  Thomas H. Gabert ,  Joseph P. Hasselbach ,  Qizhi Liu ,  Glenn C. MacDougall

IPC: H01L29/732 ,  H01L29/161 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/732 ,  H01L21/76221 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/737 ,  H01L29/7371

Abstract: Aspects of the invention provide a method of forming a bipolar junction transistor. The method includes: providing a semiconductor substrate including a uniform silicon nitride layer over an emitter pedestal, and a base layer below the emitter pedestal; applying a photomask at a first end and a second end of a base region; and performing a silicon nitride etch with the photomask to simultaneously form silicon nitride spacers adjacent to the emitter pedestal and exposing the base region of the bipolar junction transistor. The silicon nitride etch may be an end-pointed etch.

Abstract translation: 本发明的方面提供了形成双极结型晶体管的方法。 该方法包括：在发射台上设置包括均匀的氮化硅层的半导体衬底，以及在发射极底座下面的基底层; 在基区的第一端和第二端应用光掩模; 以及用所述光掩模进行氮化硅蚀刻以同时形成与所述发射极基座相邻的氮化硅间隔体，并暴露所述双极结型晶体管的基极区域。 氮化硅蚀刻可以是端点蚀刻。

公开(公告)号：US20150041956A1

公开(公告)日：2015-02-12

申请号：US14492582

申请日：2014-09-22

Applicant: International Business Machines Corporation

Inventor： Peng Cheng ,  Peter B. Gray ,  Vibhor Jain ,  Robert K. Leidy ,  Qizhi Liu

IPC: H01L29/732

CPC classification number: H01L29/732 ,  H01L21/76229 ,  H01L21/76283 ,  H01L29/66242 ,  H01L29/7378

Abstract: Device structures and design structures for a bipolar junction transistor. The device structure includes a collector region in a substrate, a plurality of isolation structures extending into the substrate and comprised of an electrical insulator, and an isolation region in the substrate. The isolation structures have a length and are arranged with a pitch transverse to the length such that each adjacent pair of the isolation structures is separated by a respective section of the substrate. The isolation region is laterally separated from at least one of the isolation structures by a first portion of the collector region. The isolation region laterally separates a second portion of the collector region from the first portion of the collector region. The device structure further includes an intrinsic base on the second portion of the collector region and an emitter on the intrinsic base. The emitter has a length transversely oriented relative to the length of the isolation structures.

Abstract translation: 双极结型晶体管的器件结构和设计结构。 器件结构包括衬底中的集电极区域，延伸到衬底中并由电绝缘体构成的多个隔离结构以及衬底中的隔离区域。 隔离结构具有长度并且以横向于长度的间距布置，使得每个相邻的一对隔离结构被基板的相应部分分开。 隔离区域通过集电区域的第一部分与隔离结构中的至少一个横向分离。 隔离区域将收集区域的第二部分与收集器区域的第一部分横向分离。 器件结构还包括在集电极区域的第二部分上的本征基极和在本征基极上的发射极。 发射极相对于隔离结构的长度具有横向定向的长度。

公开(公告)号：US20150008562A1

公开(公告)日：2015-01-08

申请号：US14497579

申请日：2014-09-26

Applicant: International Business Machines Corporation

Inventor： David L. Harame ,  Qizhi Liu

IPC: H01L29/735 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/10

CPC classification number: H01L29/735 ,  H01L21/8224 ,  H01L21/8228 ,  H01L27/0821 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/1008 ,  H01L29/16 ,  H01L29/6625 ,  H01L29/66272 ,  H01L29/7371

Abstract: Lateral PNP bipolar junction transistors and design structures for a lateral PNP bipolar junction transistor. An emitter and a collector of the lateral PNP bipolar junction transistor are comprised of p-type semiconductor material that is formed by a selective epitaxial growth process. The source and drain each directly contact a top surface of a device region used to form the emitter and collector. A base contact may be formed on the top surface and overlies an n-type base defined within the device region. The emitter is laterally separated from the collector by the base contact. Another base contact may be formed in the device region that is separated from the other base contact by the base.

Abstract translation: 横向PNP双极结晶体管和横向PNP双极结晶体管的设计结构。 横向PNP双极结晶体管的发射极和集电极由通过选择性外延生长工艺形成的p型半导体材料组成。 源极和漏极各自直接接触用于形成发射极和集电极的器件区域的顶表面。 基部触点可以形成在顶表面上并且覆盖限定在器件区域内的n型基极。 发射极通过基座触点与收集器横向分开。 另一个基底接触可以形成在由基部与另一个基部接触分离的器件区域中。

公开(公告)号：US20140231878A1

公开(公告)日：2014-08-21

申请号：US14228890

申请日：2014-03-28

Applicant: International Business Machines Corporation

Inventor： James W. Adkisson ,  David L. Harame ,  Qizhi Liu

IPC: H01L29/737

CPC classification number: H01L29/7371 ,  H01L29/0649 ,  H01L29/267 ,  H01L29/66242 ,  H01L29/7327 ,  H01L29/737 ,  H01L29/7378

Abstract: Fabrication methods, device structures, and design structures for a bipolar junction transistor. An emitter is formed in a device region defined in a substrate. An intrinsic base is formed on the emitter. A collector is formed that is separated from the emitter by the intrinsic base. The collector includes a semiconductor material having an electronic bandgap greater than an electronic bandgap of a semiconductor material of the device region.

公开(公告)号：US20140084420A1

公开(公告)日：2014-03-27

申请号：US13627179

申请日：2012-09-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： James W. Adkisson ,  Kevin K. Chan ,  David L. Harame ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L21/331 ,  H01L29/732

CPC classification number: H01L29/7371 ,  H01L21/82285 ,  H01L29/0649 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/16 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7378

Abstract: A method of forming a heterojunction bipolar transistor. The method includes providing a structure comprising at least an intrinsic base region and an emitter pedestal region. A stack is formed on the intrinsic base region. The stack comprises a polysilicon layer and a top sacrificial oxide layer. A trench is formed in the structure. The trench circumscribes the intrinsic base region and the stack. An extrinsic base is formed at two regions around the stack. The extrinsic base is formed by a selective epitaxial growth process to create a bridge over the trench. The bridge connects the two regions. An opening is provided in the stack. The opening exposes a portion of the intrinsic base region. An emitter is formed in the opening.

Abstract translation: 一种形成异质结双极晶体管的方法。 该方法包括提供包括至少本征基极区域和发射极基座区域的结构。 在本征基区上形成堆叠。 堆叠包括多晶硅层和顶部牺牲氧化物层。 在结构中形成沟槽。 沟槽围绕内在的基极区域和叠层。 在堆叠周围的两个区域形成一个非本征基。 外部基极通过选择性外延生长工艺形成，以在沟槽上形成桥。 桥梁连接两个地区。 在堆栈中提供一个开口。 开口暴露了内在基础区域的一部分。 在开口中形成发射体。

公开(公告)号：US10790369B2

公开(公告)日：2020-09-29

申请号：US16050230

申请日：2018-07-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Vibhor Jain ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L29/812 ,  H01L29/49 ,  H01L29/47 ,  H01L27/12 ,  H01L29/51

Abstract: A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

公开(公告)号：US20190341455A1

公开(公告)日：2019-11-07

申请号：US16516815

申请日：2019-07-19

Applicant: International Business Machines Corporation

Inventor： Renata Camillo-Castillo ,  David L. Harame ,  Qizhi Liu

IPC: H01L29/10 ,  H01L21/225 ,  H01L29/06 ,  H01L29/737 ,  H01L29/08 ,  H01L29/66 ,  H01L21/324

Abstract: A method includes forming a base layer on a top surface of a substrate. A dielectric layer is formed on exposed surfaces of the base layer. A hardmask layer is formed on the base layer and the dielectric layer. A pattern is formed from the hardmask with a first opening and a second opening. Portions of a dielectric layer are removed from the top surface of the base layer at positions consistent with the pattern of the first opening and the second opening to form exposed surfaces defined as a first window and a second window in the dielectric layer. Deposits of a dopant-containing layer are limited on the exposed surfaces of: a first portion on the top surface of the base layer inside of the first window, and a second portion on the top surface of the base layer inside of the second window.