公开(公告)号：US10288645B2

公开(公告)日：2019-05-14

申请号：US14755733

申请日：2015-06-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： David M. Audette ,  Sukjay J. Chey ,  Steven A. Cordes ,  Anthony D. Fortin ,  David L. Gardell ,  John R. Maher ,  Sankeerth Rajalingam ,  Frederick H. Roy, III

IPC: G01R3/00 ,  G01R31/28 ,  G01R1/073

Abstract: An organic probe substrate structure includes a daughter card; an organic laminate attached to the daughter card; and multiple probes built onto a top surface of the organic laminate.

公开(公告)号：US10168477B2

公开(公告)日：2019-01-01

申请号：US15354193

申请日：2016-11-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Aydin Babakhani ,  Steven A. Cordes ,  Jean-Olivier Plouchart ,  Scott K. Reynolds ,  Peter J. Sorce ,  Robert E. Trzcinski

IPC: H01L31/0232 ,  H01S5/183 ,  G02B6/13 ,  H01L31/18 ,  H01L27/144 ,  H01S5/022 ,  H01S5/02 ,  G02B6/42 ,  H01S5/10 ,  G02B6/12 ,  G02B6/124 ,  G02B6/30

Abstract: According to an aspect of the present principles, methods are provided for fabricating an integrated structure. A method includes forming a very large scale integration (VLSI) structure including a semiconductor layer at a top of the VLSI structure. The method further includes mounting the VLSI structure to a support structure. The method additionally includes removing at least a portion of the semiconductor layer from the VLSI structure. The method also includes attaching an upper layer to the top of the VLSI structure. The upper layer is primarily composed of a material that has at least one of a higher resistivity or a higher transparency than the semiconductor layer. The upper layer includes at least one hole for at least one of a photonic device or an electronic device. The method further includes releasing said VLSI structure from the support structure.

公开(公告)号：US20170192172A1

公开(公告)日：2017-07-06

申请号：US15466966

申请日：2017-03-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Aydin Babakhani ,  Steven A. Cordes ,  Jean-Olivier Plouchart ,  Scott K. Reynolds ,  Peter J. Sorce ,  Robert E. Trzcinski

IPC: G02B6/13 ,  G02B6/30 ,  G02B6/124 ,  G02B6/12 ,  H01L27/144

CPC classification number: G02B6/13 ,  G02B6/12004 ,  G02B6/124 ,  G02B6/30 ,  G02B6/42 ,  G02B2006/12121 ,  H01L27/1446 ,  H01L31/02327 ,  H01L31/18 ,  H01L2224/16225 ,  H01S5/021 ,  H01S5/02248 ,  H01S5/1071 ,  H01S5/183

Abstract: According to an aspect of the present principles, methods are provided for fabricating an integrated structure. A method includes forming a very large scale integration (VLSI) structure including a semiconductor layer at a top of the VLSI structure. The method further includes mounting the VLSI structure to a support structure. The method additionally includes removing at least a portion of the semiconductor layer from the VLSI structure. The method also includes attaching an upper layer to the top of the VLSI structure. The upper layer is primarily composed of a material that has at least one of a higher resistivity or a higher transparency than the semiconductor layer. The upper layer includes at least one hole for at least one of a photonic device or an electronic device. The method further includes releasing said VLSI structure from the support structure.

公开(公告)号：US09171742B2

公开(公告)日：2015-10-27

申请号：US13947543

申请日：2013-07-22

Applicant: International Business Machines Corporation

Inventor： Evan G. Colgan ,  Steven A. Cordes ,  Daniel C. Edelstein ,  Vijayeshwar D. Khanna ,  Kenneth Latzko ,  Qinghuang Lin ,  Peter J. Sorce ,  Sri M. Sri-Jayantha ,  Robert L. Wisnieff ,  Roy R. Yu

IPC: H01L21/00 ,  H01L21/50 ,  H01L25/00 ,  H01L25/065 ,  H01L29/06 ,  H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/50 ,  H01L25/0657 ,  H01L25/50 ,  H01L29/0657 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/10156 ,  H01L2924/00

Abstract: The present disclosure relates to methods and devices for manufacturing a three-dimensional chip package. A method includes forming a linear groove on an alignment rail, attaching an alignment rod to the linear groove, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail. Another method includes forming an alignment ridge on an alignment rail, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail.

Abstract translation: 本公开涉及用于制造三维芯片封装的方法和装置。 一种方法包括在对准导轨上形成直线槽，将对准杆连接到线性槽，在多个集成电路芯片上形成对准通道，并通过将多个集成电路芯片沿着 对准导轨 另一种方法包括在对准导轨上形成对准脊，在多个集成电路芯片上形成对准通道，并且通过沿对准导轨堆叠多个集成电路芯片来对准多个集成电路芯片。

公开(公告)号：US09953090B2

公开(公告)日：2018-04-24

申请号：US15585222

申请日：2017-05-03

Applicant: International Business Machines Corporation

Inventor： Steven A. Cordes ,  Debra C. Leach ,  Debra A. Loussedes ,  Patrick R. Varekamp

IPC: G06F17/30 ,  H04L29/08

CPC classification number: G06F17/30867 ,  G06F17/3051 ,  G06F17/30545 ,  H04L67/10

Abstract: Resolving a query received from a first node in a network includes accepting, by a second node in the network, ownership of the query from the first node, receiving, at the second node, an identification of a third node in the network, wherein the identification is received from a user of the second node and the user of the second node believes that a user of the third node has information necessary to resolve at least part of the query, and transferring, by the second node, ownership of the at least part of the query to the third node, wherein the accepting, the receiving, and the transferring dynamically generates a data structure that traces a propagation of the query, and the data structure is accessible to an origin of the query.

公开(公告)号：US09679023B2

公开(公告)日：2017-06-13

申请号：US14977771

申请日：2015-12-22

Applicant: International Business Machines Corporation

Inventor： Steven A. Cordes ,  Debra C. Leach ,  Debra A. Loussedes ,  Patrick R. Varekamp

IPC: G06F15/16 ,  G06F17/30 ,  H04L29/08

CPC classification number: G06F17/30867 ,  G06F17/3051 ,  G06F17/30545 ,  H04L67/10

Abstract: Resolving a query received from a first node in a network includes accepting, by a second node in the network, ownership of the query from the first node, receiving, at the second node, an identification of a third node in the network, wherein the identification is received from a user of the second node and the user of the second node believes that a user of the third node has information necessary to resolve at least part of the query, and transferring, by the second node, ownership of the at least part of the query to the third node, wherein the accepting, the receiving, and the transferring dynamically generates a data structure that traces a propagation of the query, and the data structure is accessible to an origin of the query.

公开(公告)号：US20170068050A1

公开(公告)日：2017-03-09

申请号：US15354193

申请日：2016-11-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Aydin Babakhani ,  Steven A. Cordes ,  Jean-Olivier Plouchart ,  Scott K. Reynolds ,  Peter J. Sorce ,  Robert E. Trzcinski

IPC: G02B6/13 ,  H01L31/18 ,  H01S5/02 ,  H01S5/10 ,  H01S5/022 ,  H01S5/183 ,  H01L27/144 ,  H01L31/0232

CPC classification number: G02B6/13 ,  G02B6/12004 ,  G02B6/124 ,  G02B6/30 ,  G02B6/42 ,  G02B2006/12121 ,  H01L27/1446 ,  H01L31/02327 ,  H01L31/18 ,  H01L2224/16225 ,  H01S5/021 ,  H01S5/02248 ,  H01S5/1071 ,  H01S5/183

Abstract: According to an aspect of the present principles, methods are provided for fabricating an integrated structure. A method includes forming a very large scale integration (VLSI) structure including a semiconductor layer at a top of the VLSI structure. The method further includes mounting the VLSI structure to a support structure. The method additionally includes removing at least a portion of the semiconductor layer from the VLSI structure. The method also includes attaching an upper layer to the top of the VLSI structure. The upper layer is primarily composed of a material that has at least one of a higher resistivity or a higher transparency than the semiconductor layer. The upper layer includes at least one hole for at least one of a photonic device or an electronic device. The method further includes releasing said VLSI structure from the support structure.

Abstract translation: 根据本原理的一个方面，提供了用于制造集成结构的方法。 一种方法包括形成包括VLSI结构顶部的半导体层的非常大规模的集成（VLSI）结构。 该方法还包括将VLSI结构安装到支撑结构。 该方法还包括从VLSI结构去除半导体层的至少一部分。 该方法还包括将上层附接到VLSI结构的顶部。 上层主要由具有比半导体层更高电阻率或更高透明度中的至少一种的材料组成。 上层包括用于光子器件或电子器件中的至少一个的至少一个孔。 该方法还包括从支撑结构释放所述VLSI结构。

公开(公告)号：US20150024549A1

公开(公告)日：2015-01-22

申请号：US13947543

申请日：2013-07-22

Applicant: International Business Machines Corporation

Inventor： Evan G. Colgan ,  Steven A. Cordes ,  Daniel C. Edelstein ,  Vijayeshwar D. Khanna ,  Kenneth Latzko ,  Qinghuang Lin ,  Peter J. Sorce ,  Sri M. Sri-Jayantha ,  Robert L. Wisnieff ,  Roy R. Yu

IPC: H01L21/50

CPC classification number: H01L21/50 ,  H01L25/0657 ,  H01L25/50 ,  H01L29/0657 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/10156 ,  H01L2924/00

Abstract: The present disclosure relates to methods and devices for manufacturing a three-dimensional chip package. A method includes forming a linear groove on an alignment rail, attaching an alignment rod to the linear groove, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail. Another method includes forming an alignment ridge on an alignment rail, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail.

Abstract translation: 本公开涉及用于制造三维芯片封装的方法和装置。 一种方法包括在对准导轨上形成直线槽，将对准杆连接到线性槽，在多个集成电路芯片上形成对准通道，并通过将多个集成电路芯片沿着 对准导轨 另一种方法包括在对准导轨上形成对准脊，在多个集成电路芯片上形成对准通道，并且通过沿对准导轨堆叠多个集成电路芯片来对准多个集成电路芯片。

公开(公告)号：US20140280449A1

公开(公告)日：2014-09-18

申请号：US13795063

申请日：2013-03-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Steven A. Cordes ,  Debra C. Leach ,  Debra A. Loussedes ,  Patrick R. Varekamp

IPC: H04L29/08

CPC classification number: G06F17/30867 ,  G06F17/3051 ,  G06F17/30545 ,  H04L67/10

Abstract: A method for resolving a query received from a first node in a network includes accepting, by a second node in the network, ownership of the query from the first node, receiving, at the second node, an identification of a third node in the network, wherein the identification is received from a user of the second node and the user of the second node believes that a user of the third node has information necessary to resolve at least part of the query, and transferring, by the second node, ownership of the at least part of the query to the third node, wherein the accepting, the receiving, and the transferring dynamically generates a data structure that traces a propagation of the query, and the data structure is accessible to an origin of the query.

Abstract translation: 用于解析从网络中的第一节点接收到的查询的方法包括由网络中的第二节点接收来自第一节点的查询的所有权，在第二节点处接收网络中的第三节点的标识 其中，从所述第二节点的用户接收所述标识，并且所述第二节点的用户认为所述第三节点的用户具有解析所述查询的至少一部分所必需的信息，并且由所述第二节点转移所述第二节点的所有权 对第三节点的查询的至少一部分，其中接受，接收和传送动态地生成跟踪查询的传播的数据结构，并且数据结构可以由查询的来源访问。