公开(公告)号：US20220367797A1

公开(公告)日：2022-11-17

申请号：US17876237

申请日：2022-07-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Wanki Kim ,  Fabio Carta ,  Chung H. Lam ,  Robert L. Bruce

IPC: H01L45/00 ,  H01L27/24

Abstract: A method for fabricating a semiconductor device includes forming air gaps within respective dielectric layer portions to reduce thermal cross-talk between adjacent bits. Each of the dielectric portions is formed on a substrate each adjacent to sidewall liners formed on sidewalls of a phase change memory (PCM) layer. The method further includes forming a pillar including the sidewall liners and the PCM layer, and forming a selector layer on the pillar and the dielectric portions.

公开(公告)号：US20210399047A1

公开(公告)日：2021-12-23

申请号：US16907065

申请日：2020-06-19

Applicant: International Business Machines Corporation

Inventor： Ning Li ,  Devendra K. Sadana ,  Wanki Kim

IPC: H01L27/24 ,  H01L29/66 ,  H01L29/861 ,  H01L45/00 ,  G11C13/00

Abstract: A diode is made of a p-type layer and an n-type layer connected in series between a bottom and top electrode. The p-type and n-type layers have a thickness below 20 nm. A p-type dopant concentration and an n-type dopant concentration are high enough to keep a total resistance across the diode at less than 250Ω when the diode is forward biased while still retaining the characteristics of a diode. In some embodiments, the ratio of an ON current to an OFF current is greater than 2.5×104. Alternate embodiments of the diode, arrays of diodes and methods of making diodes are disclosed. Example arrays include memory arrays using diodes and phase change memories (PCMs) connected in series as array elements. The arrays can be stacked in layers and can be made/embodied in the back-end-of-the line (BEOL).

公开(公告)号：US11055459B2

公开(公告)日：2021-07-06

申请号：US16433675

申请日：2019-06-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qianwen Chen ,  Li-Wen Hung ,  Wanki Kim ,  John U. Knickerbocker ,  Kenneth P. Rodbell ,  Robert L. Wisnieff

IPC: H01L25/065 ,  H01L25/07 ,  G06F30/331 ,  H01L23/31 ,  H01L25/00 ,  H01L23/00 ,  H01L21/683 ,  H01L25/11 ,  H01L21/56 ,  H01L25/18 ,  G06F15/78 ,  G06F15/80

Abstract: A method of forming an electrical device is provided that includes forming microprocessor devices on a microprocessor die; forming memory devices on an memory device die; forming component devices on a component die; and forming a plurality of packing devices on a packaging die. Transferring a plurality of each of said microprocessor devices, memory devices, component devices and packaging components to a supporting substrate, wherein the packaging components electrically interconnect the memory devices, component devices and microprocessor devices in individualized groups. Sectioning the supporting substrate to provide said individualized groups of memory devices, component devices and microprocessor devices that are interconnected by a packaging component.

公开(公告)号：US20210050384A1

公开(公告)日：2021-02-18

申请号：US16542929

申请日：2019-08-16

Applicant: International Business Machines Corporation

Inventor： Fabio Carta ,  Matthew J. BrightSky ,  Bahman Hekmatshoartabari ,  Asit Ray ,  Wanki Kim

IPC: H01L27/24 ,  H01L45/00 ,  H01L29/04 ,  H01L29/16 ,  H01L29/861 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3213

Abstract: A method of fabricating an access device in a crosspoint memory array structure during BEOL processing includes: forming at least a first doped semiconductor layer on an upper surface of a first conductive layer, the first doped semiconductor layer being in electrical connection with the first conductive layer; exposing at least a portion of the first doped semiconductor layer to a directed energy source to cause localized annealing in the first doped semiconductor layer to activate a dopant of a first conductivity type in the first doped semiconductor layer, thereby converting at least a portion of the first doped semiconductor layer into a polycrystalline layer; forming a second conductive layer over a least a portion of the first doped semiconductor layer; and etching the first doped semiconductor layer and the first and second conductive layers to form an access device that is self-aligned with the first and second conductive layers.

公开(公告)号：US10892413B2

公开(公告)日：2021-01-12

申请号：US15408392

申请日：2017-01-17

Applicant: International Business Machines Corporation

Inventor： Robert L. Bruce ,  Fabio Carta ,  Wanki Kim ,  Chung H. Lam

IPC: H01L45/00 ,  H01L27/24

Abstract: A phase change memory array and method for fabricating the same. The phase change memory array includes a plurality of bottom electrodes, top electrodes, and memory pillars. Each of the memory pillars includes phase change material surrounded by a dielectric casing. The phase change material is positioned between, and in series circuit with, a respective bottom electrode from the bottom electrodes and a respective top electrode from the top electrodes. A continuous layer of selector material is positioned between the memory pillars and the plurality of bottom electrodes. The selector material is configured to conduct electricity only when a voltage across the selector material exceeds a voltage threshold.

公开(公告)号：US10380284B2

公开(公告)日：2019-08-13

申请号：US15626582

申请日：2017-06-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qianwen Chen ,  Li-Wen Hung ,  Wanki Kim ,  John U. Knickerbocker ,  Kenneth P. Rodbell ,  Robert L. Wisnieff

IPC: G06F17/50 ,  G06F15/78 ,  H01L25/00 ,  H01L23/31 ,  H01L23/00 ,  H01L21/683 ,  H01L25/065 ,  H01L25/11 ,  H01L25/07 ,  H01L21/56 ,  H01L25/18 ,  G06F15/80

Abstract: A method of forming an electrical device is provided that includes forming microprocessor devices on a microprocessor die; forming memory devices on an memory device die; forming component devices on a component die; and forming a plurality of packing devices on a packaging die. Transferring a plurality of each of said microprocessor devices, memory devices, component devices and packaging components to a supporting substrate, wherein the packaging components electrically interconnect the memory devices, component devices and microprocessor devices in individualized groups. Sectioning the supporting substrate to provide said individualized groups of memory devices, component devices and microprocessor devices that are interconnected by a packaging component.

公开(公告)号：US20180331284A1

公开(公告)日：2018-11-15

申请号：US15590014

申请日：2017-05-09

Applicant: International Business Machines Corporation ,  MACRONIX INTERNATIONAL CO., LTD

Inventor： Matthew J. BrightSky ,  Fabio Carta ,  Huai-Yu Cheng ,  Wanki Kim

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/141 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1608 ,  H01L45/1666 ,  H01L45/1683

Abstract: A memory access device that includes a first terminal with a first terminal workfunction and a chalcogenide-based selector layer with a first surface and a second surface opposite the first surface. A first control metal layer is positioned in physical and electrical contact with the first terminal and the first surface of the chalcogenide-based selector layer. The first control metal layer includes a first control workfunction different than the first terminal workfunction. A second terminal with a second terminal workfunction is positioned proximate the second surface of the chalcogenide-based selector layer.

公开(公告)号：US20160125936A1

公开(公告)日：2016-05-05

申请号：US14533495

申请日：2014-11-05

Applicant: International Business Machines Corporation

Inventor： Matthew J. BrightSky ,  SangBum Kim ,  Wanki Kim ,  Chung H. Lam

IPC: G11C13/00

CPC classification number: G11C13/0004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0078 ,  G11C2013/0083 ,  G11C2013/0092 ,  H01L45/06 ,  H01L45/144

Abstract: A memory device that includes a phase change material. The phase change material is programmable to a metastable set state and metastable reset state. Furthermore, the phase change material includes an initial state with an initial electrical resistance between the set electrical resistance and the reset electrical resistance. The initial state is at a lower potential energy than the set state and the reset state. Thus, the electrical resistance of the phase change material programmed to the set state or the reset state drifts toward the initial electrical resistance over time. The memory device also includes a first electrode electrically coupled to a first area of the phase change material, and a second electrode electrically coupled to a second area of the phase change material.

公开(公告)号：US12185646B2

公开(公告)日：2024-12-31

申请号：US18082189

申请日：2022-12-15

Applicant: International Business Machines Corporation

Inventor： Ning Li ,  Wanki Kim ,  Devendra K. Sadana

IPC: H10N70/00

Abstract: A phase change memory (PCM) structure configured for performing a gradual reset operation includes first and second electrodes and a phase change material layer disposed between the first and second electrodes. The PCM structure further includes a thermal insulation layer disposed on at least sidewalls of the first and second electrodes and phase change material layer. The thermal insulation layer is configured to provide non-uniform heating of the phase change material layer. Optionally, the thermal insulation layer may be formed as an air gap. The PCM structure may be configured having the first and second electrodes aligned in a vertical or a lateral arrangement.

公开(公告)号：US11557343B2

公开(公告)日：2023-01-17

申请号：US17304503

申请日：2021-06-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Fabio Carta ,  Matthew Joseph BrightSky ,  Wanki Kim ,  Maxence Bouvier ,  SangBum Kim

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/54 ,  G06N3/06

Abstract: According to one embodiment, a method, computer system, and computer program product for increasing linearity of a weight update of a phase change memory (PCM) cell is provided. The present invention may include applying a RESET pulse to amorphize the phase change material of the PCM cell; responsive to applying the RESET pulse, applying an incubation pulse to the PCM cell; and applying a plurality of partial SET pulses to incrementally increase the conductance of the PCM cell.