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公开(公告)号：US09837408B1
公开(公告)日：2017-12-05
申请号：US15278420
申请日：2016-09-28
Applicant: International Business Machines Corporation
Inventor： Zhenxing Bi , Kangguo Cheng , Peng Xu , Zheng Xu
IPC: H01L27/088 , H01L21/8234 , H01L21/02 , H01L21/306 , H01L29/16 , H01L29/78
CPC classification number: H01L27/0886 , H01L21/02381 , H01L21/02532 , H01L21/30604 , H01L21/3086 , H01L21/823431 , H01L21/823437 , H01L21/823807 , H01L21/823821 , H01L27/0924 , H01L29/1054 , H01L29/16 , H01L29/66795 , H01L29/7849 , H01L29/7851
Abstract: Embodiments are directed to a method of forming features of a semiconductor device. The method includes forming a first feature including a first type of semiconductor material, which can be tensile or can have compressive strain. The method further includes forming an enclosure structure including a second type of semiconductor material, wherein the first feature includes first feature sidewall surfaces extending around a circumference of the first feature. The enclosure structure is adjacent at least a portion of the first feature sidewall surfaces and extends around the circumference of the first feature.
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公开(公告)号：US09741485B2
公开(公告)日：2017-08-22
申请号：US14823113
申请日：2015-08-11
Applicant: International Business Machines Corporation
Inventor： Pinping Sun , Chengwen Pei , Zheng Xu
CPC classification number: H01F27/362 , H01F17/0013 , H01F27/2804 , H01F27/2871 , H01F27/289 , H01F41/041 , H01F2017/008 , H01F2027/2809 , H01L23/60 , H01L23/645 , H01L2924/0002 , Y10T29/4902 , H01L2924/00
Abstract: A reconfigurable multi-stack inductor formed within a semiconductor structure may include a first inductor structure located within a first metal layer of the semiconductor structure, a first ground shielding structure located within the first metal layer that is electrically isolated from and circumferentially bounds the first inductor structure, and a second inductor structure located within a second metal layer of the semiconductor structure, whereby the second inductor structure is electrically coupled to the first inductor structure. A second ground shielding structure located within the second metal layer is electrically isolated from and circumferentially bounds the second inductor structure, whereby the first and second inductor generate a first inductance value based on the first ground shielding structure and second ground shielding structure being coupled to ground, and the first and second inductor generate a second inductance value based on the first ground shielding structure and second ground shielding structure electrically floating.
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公开(公告)号：US20230089257A1
公开(公告)日：2023-03-23
申请号：US17481180
申请日：2021-09-21
Applicant: International Business Machines Corporation
Inventor： Juntao Li , Kangguo Cheng , Dexin Kong , Zheng Xu
IPC: H01L45/00
Abstract: Embodiments disclosed herein include an RRAM cell. The RRAM cell may include a first nanowire electrically connected to a first wordline electrode. The nanowire may include a first sharpened point distal from the first wordline electrode. The RRAM cell may also include a metal contact electrically connected to a bitline electrode and a high-κ dielectric layer directly between the nanowire and the metal contact.
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公开(公告)号：US20230074224A1
公开(公告)日：2023-03-09
申请号：US17469203
申请日：2021-09-08
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Juntao Li , Kangguo Cheng , Dexin Kong , Zheng Xu
IPC: H01L45/00
Abstract: Methods of forming a settable resistance device, settable resistance devices, and neuromorphic computing devices include isotropically etching a stack of layers, the stack of layers having an insulator layer in contact with a conductor layer, to selectively form divots in exposed sidewalls of the conductor layer. The stack of layers is isotropically etched to selectively form divots in exposed sidewalls of the insulator layer, thereby forming a tip at an interface between the insulator layer and the conductor layer. A dielectric layer is formed over the stack of layers to cover the tip. An electrode is formed over the dielectric layer, such that the dielectric layer is between the electrode and the tip.
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公开(公告)号：US11165248B2
公开(公告)日：2021-11-02
申请号：US16663677
申请日：2019-10-25
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Qianwen Chen , Yang Liu , Dongbing Shao , Zheng Xu
Abstract: A method forms an air gap metal tip structure for (ESD) protection. The method forms an air chamber, from an upper substrate and a lower substate disposed below the upper substrate, within which a first metal tip and a second metal tip are disposed. The first and second metal tips are disposed along at least one horizontal axis parallel to the upper and lower substrates. The chamber includes a portion between points of the metal tips, such that oxygen trapped in the chamber is converted into ozone responsive to an arc between the metal tips to dissipate the arc, and the ozone is decomposed back into the oxygen responsive to an arc absence between the metal tips to maintain the ESD protection for subsequent arcs. An under fill level is disposed between the lower and upper substrates, and above one or more layers having the first and second metal tips.
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Patent Agency Ranking
公开(公告)号：US11133670B2
公开(公告)日：2021-09-28
申请号：US16663715
申请日：2019-10-25
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Qianwen Chen , Yang Liu , Dongbing Shao , Zheng Xu
Abstract: An air gap metal tip structure is provided for (ESD) protection. The structure includes first and second metal tips disposed along at least one horizontal axis that is parallel to a upper substrate and a lower substrate. The structure includes an air chamber formed between the upper and lower substrate within which the first metal tip and the second metal tip are disposed. The air chamber includes a portion between points of the metal tips. The structure includes an under fill level disposed between the lower and upper substrates, and above one or more layers having the metal tips. Oxygen trapped in the air chamber is converted into ozone responsive to an arc between the metal tips to dissipate the arc, and the ozone is decomposed back into the oxygen responsive to an absence of the arc between the metal tips to maintain the ESD protection for subsequent arcs.
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公开(公告)号：US20210280514A1
公开(公告)日：2021-09-09
申请号：US16808693
申请日：2020-03-04
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Zheng Xu , Kangguo Cheng , Dexin Kong , Juntao Li
IPC: H01L23/525 , H01L23/528
Abstract: A semiconductor structure is provided. The structure includes a RRAM cell having a first end and a second end. The second end is connected to a first potential. The structure includes a decoupling capacitor having a first end connected in series with the first end of the RRAM cell and a second end connected to a second potential. The structure includes a FET arranged across the capacitor to form a bridged capacitor by having a FET source connected to the first end of the capacitor and a FET drain connected to the second end of the capacitor. A paired activation and subsequent deactivation of the FET enables a short protection mode of the capacitor that provides a series resistance above a threshold amount, between the second potential and the first end of the RRAM cell, responsive to a detected short of the capacitor from the supply to the first potential.
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公开(公告)号：US10985236B2
公开(公告)日：2021-04-20
申请号：US16774194
申请日：2020-01-28
Applicant: International Business Machines Corporation
Inventor： Zhenxing Bi , Kangguo Cheng , Wei Wang , Zheng Xu
IPC: H01L21/324 , H01L21/02 , H01L21/265 , H01L21/306 , H01L21/3105 , H01L49/02
Abstract: A method of forming an integrated circuit device having a nanosheet resistor includes forming a nanosheet structure having alternating sheets of silicon and silicon germanium. An ion implantation is performed on the nanosheet structure. A thermal anneal is performed on the nanosheet structure. A dielectric oxide is placed around the nanosheet structure. A first contact and a second contact are coupled to the nanosheet structure to form a resistor between the first contact and the second contact. Other embodiments are also described herein.
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公开(公告)号：US20200380088A1
公开(公告)日：2020-12-03
申请号：US16427321
申请日：2019-05-30
Applicant: International Business Machines Corporation
Inventor： Jing Sha , Dongbing Shao , Yufei Wu , Zheng Xu
Abstract: A method for predicting local layout effect in a circuit design pattern includes obtaining a plurality of circuit design patterns, generating layout images from the circuit design patterns, extracting feature vectors from the layout images by processing the layout images in a computer vision machine learning algorithm, comparing the feature vector extracted from a selected layout image to clusters of feature vectors extracted from the layout images, wherein the clusters of feature vectors include an in-range cluster and an outlier cluster, and labelling a circuit design pattern corresponding to the selected layout image, for which threshold voltage has not been experimentally measured, as being an in-range circuit design pattern or an outlier circuit design pattern, in response to the selected layout image respectively correlating with the in-range cluster or with the outlier cluster.
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公开(公告)号：US10831973B2
公开(公告)日：2020-11-10
申请号：US16682413
申请日：2019-11-13
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Dongbing Shao , Zheng Xu , Lawrence A. Clevenger
IPC: G06F9/455 , G06F17/50 , G06F30/394 , G06F30/398 , G06F111/04 , G06F111/20
Abstract: A method is presented for incorporating skip vias in a place and route flow of an integrated circuit design. The method includes employing a place and route tool to add the skip vias, each skip via extending through a metallization layer to electrically connect a metal layer above the metallization layer to a metal layer below the metallization layer and, when a violation of a design rule is detected due to the addition of one or more of the skip vias, substituting skip vias that violate the design rule with a standard via.
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