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    FORMING FIELD EFFECT TRANSISTOR DEVICE SPACERS
    21.
    发明申请
    FORMING FIELD EFFECT TRANSISTOR DEVICE SPACERS 有权
    形成场效应晶体管器件间隔器

    公开(公告)号：US20170040453A1

    公开(公告)日：2017-02-09

    申请号：US14817504

    申请日：2015-08-04

    申请人： International Business Machines Corporation ,  GlobalFoundries, Inc.

    发明人： Rama Kambhampati ,  Junli Wang ,  Ruilong Xie ,  Tenko Yamashita

    IPC分类号： H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238

    CPC分类号： H01L27/0924 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/7848

    摘要： A method for forming field effect transistors comprises forming a first dummy gate stack over a first fin, forming a second dummy gate stack over a second fin, depositing a first layer of spacer material on the first dummy gate stack, the first fin, the second dummy gate stack, and the second fin, patterning a first masking layer on the first dummy gate stack and the first fin, etching to remove portions of the first layer of spacer material and form a spacer adjacent to the second dummy gate stack, removing the first masking layer, epitaxially growing a silicon material on the second fin, depositing a layer of oxide material on the first layer of spacer material, the first epitaxial material and the second dummy gate stack, and depositing a second layer of spacer material on the layer of oxide material.

    摘要翻译： 一种用于形成场效应晶体管的方法包括在第一鳍上形成第一虚拟栅极堆叠，在第二鳍片上形成第二虚拟栅极叠层，在第一伪栅极叠层上沉积第一层间隔物材料， 虚拟栅极堆叠和第二鳍片，在第一伪栅极堆叠和第一鳍片上构图第一掩模层，蚀刻以去除第一层间隔物材料的部分并形成邻近第二伪栅极叠层的间隔区， 第一掩模层，在所述第二鳍上外延生长硅材料，在所述第一隔离层材料层上沉积氧化物层，所述第一外延材料和所述第二伪栅极堆叠，以及在所述层上沉积第二隔离层材料层 的氧化物质。

    Forming field effect transistor device spacers
    22.
    发明授权
    Forming field effect transistor device spacers 有权
    形成场效应晶体管器件间隔物

    公开(公告)号：US09548388B1

    公开(公告)日：2017-01-17

    申请号：US14817504

    申请日：2015-08-04

    申请人： International Business Machines Corporation ,  GlobalFoundries, Inc.

    发明人： Rama Kambhampati ,  Junli Wang ,  Ruilong Xie ,  Tenko Yamashita

    IPC分类号： H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66

    CPC分类号： H01L27/0924 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/7848

    摘要： A method for forming field effect transistors comprises forming a first dummy gate stack over a first fin, forming a second dummy gate stack over a second fin, depositing a first layer of spacer material on the first dummy gate stack, the first fin, the second dummy gate stack, and the second fin, patterning a first masking layer on the first dummy gate stack and the first fin, etching to remove portions of the first layer of spacer material and form a spacer adjacent to the second dummy gate stack, removing the first masking layer, epitaxially growing a silicon material on the second fin, depositing a layer of oxide material on the first layer of spacer material, the first epitaxial material and the second dummy gate stack, and depositing a second layer of spacer material on the layer of oxide material.

    摘要翻译： 一种用于形成场效应晶体管的方法包括在第一鳍上形成第一虚拟栅极堆叠，在第二鳍片上形成第二虚拟栅极叠层，在第一伪栅极叠层上沉积第一层间隔物材料， 虚拟栅极堆叠和第二鳍片，在第一伪栅极堆叠和第一鳍片上构图第一掩模层，蚀刻以去除第一层间隔物材料的部分并形成邻近第二伪栅极叠层的间隔区， 第一掩模层，在所述第二鳍上外延生长硅材料，在所述第一隔离层材料层上沉积氧化物层，所述第一外延材料和所述第二伪栅极堆叠，以及在所述层上沉积第二隔离层材料层 的氧化物质。

    TRANSISTORS COMPRISING DOPED REGION-GAP-DOPED REGION STRUCTURES AND METHODS OF FABRICATION
    26.
    发明申请
    TRANSISTORS COMPRISING DOPED REGION-GAP-DOPED REGION STRUCTURES AND METHODS OF FABRICATION 有权
    包含区域划分区域结构的晶体管和制造方法

    公开(公告)号：US20160020335A1

    公开(公告)日：2016-01-21

    申请号：US14334950

    申请日：2014-07-18

    申请人： GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

    发明人： Steven J. Bentley ,  Ajey Poovannummoottil Jacob ,  Chia-Yu Chen ,  Tenko Yamashita

    IPC分类号： H01L29/808 ,  H01L29/45 ,  H01L29/66

    CPC分类号： H01L29/495 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02532 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/167 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/78

    摘要： Embodiments of the present invention provide transistors with controlled junctions and methods of fabrication. A dummy spacer is used during the majority of front end of line (FEOL) processing. Towards the end of the FEOL processing, the dummy spacers are removed and replaced with a final spacer material. Embodiments of the present invention allow the use of a very low-k material, which is highly thermally-sensitive, by depositing it late in the flow. Additionally, the position of the gate with respect to the doped regions is highly controllable, while dopant diffusion is minimized through reduced thermal budgets. This allows the creation of extremely abrupt junctions whose surface position is defined using a sacrificial spacer. This spacer is then removed prior to final gate deposition, allowing a fixed gate overlap that is defined by the spacer thickness and any diffusion of the dopant species.

    摘要翻译： 本发明的实施例提供具有受控结的晶体管和制造方法。 在大多数前端（FEOL）处理中使用虚拟间隔器。 在FEOL处理结束之后，去除虚拟间隔物并用最后的间隔物材料代替。 本发明的实施例允许使用非常低k的材料，其通过在流动中较晚沉积而具有高度热敏感性。 此外，栅极相对于掺杂区域的位置是高度可控的，而掺杂剂扩散通过减少的热预算被最小化。 这允许创建极其突出的接头，其表面位置使用牺牲隔离物限定。 然后在最终栅极沉积之前去除该间隔物，允许由间隔物厚度和掺杂剂物质的任何扩散限定的固定栅极重叠。

    TEST MACRO FOR USE WITH A MULTI-PATTERNING LITHOGRAPHY PROCESS
    28.
    发明申请
    TEST MACRO FOR USE WITH A MULTI-PATTERNING LITHOGRAPHY PROCESS 有权
    使用多模式图像处理的测试方法

    公开(公告)号：US20150140697A1

    公开(公告)日：2015-05-21

    申请号：US14607160

    申请日：2015-01-28

    申请人： International Business Machines Corporation ,  GlobalFoundries, Inc.

    发明人： Tenko Yamashita ,  Chun-Chen Yeh ,  Jin Cho ,  Hui Zang

    IPC分类号： H01L21/66 ,  H01L21/8234

    CPC分类号： H01L22/14 ,  G03F7/70466 ,  H01L21/823431 ,  H01L22/10 ,  H01L22/12 ,  H01L22/34

    摘要： A method for forming an integrated circuit having a test macro using a multiple patterning lithography process (MPLP) is provided. The method includes forming an active area of the test macro having a first and second gate region during a first step of MPLP, and forming a first and second source/drain regions in the active area during a second step of the MPLP. The method also includes forming a first contact connected to the first gate region, a second contact connected to the second gate region, a third contact connected to the first source/drain region, and a forth contact connected to the source/drain region and determining if an overlay shift occurred between the first step and the second step of the step of the MPLP by testing for a short between one or more of the first contact, the second contact, the third contact, or the fourth contact.

    摘要翻译： 提供了一种使用多重图案化光刻工艺（MPLP）形成具有测试宏的集成电路的方法。 该方法包括在MPLP的第一步骤期间形成具有第一和第二栅极区的测试宏的有源区，以及在MPLP的第二步骤期间在有源区中形成第一和第二源/漏区。 该方法还包括形成连接到第一栅极区域的第一触点，连接到第二栅极区域的第二触点，连接到第一源极/漏极区域的第三触点和连接到源极/漏极区域的第四触点和确定 如果通过测试第一接触，第二接触，第三接触或第四接触中的一个或多个之间的短路，在MPLP的步骤的第一步骤和第二步骤之间发生覆盖移位。

    Dual metal-insulator-semiconductor contact structure and formulation method
    29.
    发明授权
    Dual metal-insulator-semiconductor contact structure and formulation method 有权

    公开(公告)号：US10833019B2

    公开(公告)日：2020-11-10

    申请号：US16668409

    申请日：2019-10-30

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

    发明人： Takashi Ando ,  Hiroaki Niimi ,  Tenko Yamashita

    IPC分类号： H01L29/78 ,  H01L23/535 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/768 ,  H01L29/51 ,  H01L23/485 ,  H01L21/285 ,  H01L29/66

    摘要： A method of making a semiconductor device includes forming a first source/drain trench and a second source/drain trench over a first and second source/drain region, respectively; forming a first silicon dioxide layer in the first source/drain trench and a second silicon dioxide layer in the second source/drain trench; forming a first source/drain contact over the first source/drain region, the first source/drain contact including a first tri-layer contact disposed between the first silicon dioxide layer and a first conductive material; and forming a second source/drain contact over the second source/drain region, the second source/drain contact including a second tri-layer contact disposed between the second silicon dioxide layer and a second conductive material; wherein the first tri-layer contact includes a first metal oxide layer in contact with the first silicon dioxide layer, and the second tri-layer contact includes a second metal oxide layer in contact with the second silicon dioxide layer.

    Width adjustment of stacked nanowires
    30.
    发明授权
    Width adjustment of stacked nanowires 有权

    公开(公告)号：US10749038B2

    公开(公告)日：2020-08-18

    申请号：US16057579

    申请日：2018-08-07

    申请人： International Business Machines Corporation ,  Globalfoundries Inc.

    发明人： Kangguo Cheng ,  Xin Miao ,  Ruilong Xie ,  Tenko Yamashita

    IPC分类号： H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

    摘要： In one aspect, a method of forming a semiconductor device includes the steps of: forming an alternating series of sacrificial/active layers on a wafer and patterning it into at least one nano device stack; forming a dummy gate on the nano device stack; patterning at least one upper active layer in the nano device stack to remove all but a portion of the at least one upper active layer beneath the dummy gate; forming spacers on opposite sides of the dummy gate covering the at least one upper active layer that has been patterned; forming source and drain regions on opposite sides of the nano device stack, wherein the at least one upper active layer is separated from the source and drain regions by the spacers; and replacing the dummy gate with a replacement gate. A masking process is also provided to tailor the effective device width of select devices.