公开(公告)号：US20210358836A1

公开(公告)日：2021-11-18

申请号：US17386793

申请日：2021-07-28

Applicant: Infineon Technologies AG

Inventor： Thomas Stoek ,  Dirk Ahlers ,  Stefan Macheiner

IPC: H01L23/495 ,  H01L23/42 ,  H01L23/31

Abstract: A molded semiconductor package includes a mold compound, a plurality of leads each having a first end embedded in the mold compound and a second end protruding from a side face of the mold compound, and a semiconductor die embedded in the mold compound and electrically connected, within the mold compound, to the plurality of leads. The second end of each lead of the plurality of leads has a bottom surface facing in a same direction as a bottom main surface of the mold compound. Each lead of the plurality of leads has a negative standoff relative to the bottom main surface of the mold compound.

公开(公告)号：US10700061B2

公开(公告)日：2020-06-30

申请号：US15351816

申请日：2016-11-15

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Dirk Ahlers ,  Till Schloesser

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H03K17/687

Abstract: A semiconductor device includes a first transistor and a second transistor in a semiconductor substrate. The first transistor includes a first drain contact electrically connected to a first drain region, the first drain contact including a first drain contact portion and a second drain contact portion. The first drain contact portion includes a drain conductive material in direct contact with the first drain region. The second transistor includes a second source contact electrically connected to a second source region. The second source contact includes a first source contact portion and a second source contact portion. The first source contact portion includes a source conductive material in direct contact with the second source region.

公开(公告)号：US10586792B2

公开(公告)日：2020-03-10

申请号：US16236741

申请日：2018-12-31

Applicant: Infineon Technologies AG

Inventor： Dirk Ahlers ,  Markus Zundel ,  Peter Brandl ,  Kurt Matoy ,  Thomas Ostermann

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/06 ,  H01L29/786 ,  H01L29/40 ,  H01L49/02 ,  H01L29/739 ,  H01L29/808

Abstract: A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area.

公开(公告)号：US10276706B2

公开(公告)日：2019-04-30

申请号：US15132709

申请日：2016-04-19

Applicant: Infineon Technologies AG

Inventor： Dirk Ahlers ,  Markus Zundel ,  Dietrich Bonart ,  Ludger Borucki

IPC: H01L29/78 ,  H02J7/00 ,  H01L29/36 ,  H01L29/739 ,  H01L29/08 ,  H01L23/051 ,  H01L29/06 ,  H01L29/10 ,  H02J7/24 ,  H01L29/861 ,  H01L23/24 ,  H02J7/14

Abstract: A gated diode in a press-fit housing includes a base configured to be press-fit into an opening of a diode carrier plate and including a pedestal portion with a first flat surface, and a head wire including a head portion with a second flat surface and a wire portion. The base and the head wire form parts of the press-fit housing. The gated diode in the press-fit housing further includes a semiconductor die, a first solder layer engaging and electrically connecting the semiconductor die with the first flat surface of the base, and a second solder layer engaging and electrically connecting the semiconductor die with the second flat surface of the head wire.

公开(公告)号：US20180114788A1

公开(公告)日：2018-04-26

申请号：US15792492

申请日：2017-10-24

Applicant: Infineon Technologies AG

Inventor： Dirk Ahlers ,  Markus Zundel ,  Peter Brandl ,  Kurt Matoy ,  Thomas Ostermann

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/0292 ,  H01L27/0255 ,  H01L27/0288 ,  H01L27/0296 ,  H01L28/20 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/7395 ,  H01L29/7803 ,  H01L29/7813 ,  H01L29/78618 ,  H01L29/8083

Abstract: A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area.

公开(公告)号：US20170287820A1

公开(公告)日：2017-10-05

申请号：US15089668

申请日：2016-04-04

Applicant: Infineon Technologies AG

Inventor： Dirk Ahlers ,  Markus Dinkel

IPC: H01L23/495 ,  H02M7/44 ,  H01L21/56 ,  H02M7/00 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L23/49575 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L2224/0603 ,  H01L2224/40245 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/49113 ,  H02M7/003 ,  H02M7/44 ,  H02M7/5387

Abstract: A semiconductor package includes a substrate, a first transistor die secured to the substrate and a second transistor die secured to the substrate. The first transistor die has a source terminal at a bottom side of the first transistor die which faces the substrate and a drain terminal and a gate terminal at a top side of the first transistor die which faces away from the substrate. The second transistor die has a drain terminal at a bottom side of the second transistor die which faces the substrate and a source terminal and a gate terminal at a top side of the second transistor die which faces away from the substrate. The package also includes a common electrical connection between the drain terminal of the first transistor die and the source terminal of the second transistor die.

公开(公告)号：US20160126197A1

公开(公告)日：2016-05-05

申请号：US14932548

申请日：2015-11-04

Applicant: Infineon Technologies AG

Inventor： Kurt Matoy ,  Dirk Ahlers ,  Ulrike Fastner ,  Petra Fischer ,  Karl-Heinz Gasser ,  Stephan Henneck ,  Stefan Krivec ,  Florian Weilnboeck

IPC: H01L23/00 ,  H01L23/495 ,  H01L29/45 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/32 ,  H01L24/83 ,  H01L29/45 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/40245 ,  H01L2224/8321 ,  H01L2224/83815 ,  H01L2924/014 ,  H01L2924/3511 ,  H01L2924/37001

Abstract: A semiconductor device includes a semiconductor chip having a first main surface and a second main surface. A chip electrode is disposed on the first main surface. The chip electrode includes a first metal layer and wherein the first metal layer is arranged between the semiconductor chip and the second metal layer.

Abstract translation: 半导体器件包括具有第一主表面和第二主表面的半导体芯片。 芯片电极设置在第一主表面上。 芯片电极包括第一金属层，并且其中第一金属层布置在半导体芯片和第二金属层之间。