公开(公告)号：US20160179610A1

公开(公告)日：2016-06-23

申请号：US14578413

申请日：2014-12-20

申请人： Intel Corporation

发明人： Brian S. Morris ,  Bill Nale ,  Robert G. Blankenship ,  Eric L. Hendrickson

IPC分类号： G06F11/08 ,  G06F11/16

CPC分类号： G06F11/08 ,  G06F11/1625 ,  G06F11/1654 ,  G06F11/167 ,  G06F13/00 ,  H04L1/00 ,  H04L1/0061 ,  H04L1/0082 ,  H04L1/1838 ,  H04L2001/0097

摘要： Data is sent from a memory buffer device to a host device over a link. An error in the data is determined. A read response cancellation signal is sent to the host device to indicate the error to the host device, where the read response cancellation signal is to be sent subsequent to the data being sent from the memory buffer device to the host device.

摘要翻译： 数据通过链路从内存缓冲设备发送到主机设备。 确定数据中的错误。 读取响应消除信号被发送到主机设备以向主机设备指示错误，其中在将数据从存储器缓冲器件发送到主机设备之后要发送读取响应消除信号。

公开(公告)号：US11990172B2

公开(公告)日：2024-05-21

申请号：US18213231

申请日：2023-06-22

申请人： Intel Corporation

发明人： Bill Nale ,  Christopher E. Cox

IPC分类号： G11C11/406 ,  G06F3/06 ,  G11C11/4096

CPC分类号： G11C11/40611 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G11C11/4096 ,  G11C11/40618

摘要： A memory device with internal row hammer mitigation couples to a memory controller. The memory controller or host can assist with row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an extra refresh command the memory device can perform refresh for row hammer mitigation instead of refresh for standard data integrity. The memory controller can keep track of the number of activate commands sent to the memory device, and in response to a threshold number of activate commands, the memory controller sends the additional refresh command. With the extra refresh command the memory device can refresh the potential victim rows of a potential aggressor row, instead of simply refreshing a row that has not been accessed for a period of time.

公开(公告)号：US11790976B2

公开(公告)日：2023-10-17

申请号：US17666452

申请日：2022-02-07

申请人： Intel Corporation

发明人： Christopher E. Cox ,  Bill Nale

IPC分类号： G11C7/10 ,  G11C11/406 ,  G06F3/06 ,  G11C11/4093 ,  G11C29/02

CPC分类号： G11C11/40615 ,  G06F3/0659 ,  G11C7/10 ,  G11C7/1057 ,  G11C11/4093 ,  G11C29/021 ,  G11C29/022 ,  G11C29/028 ,  G11C29/023 ,  G11C2207/2254

摘要： A memory device is described. The memory device includes logic circuitry to perform calibrations of resistive network terminations and data drivers of the memory device while the memory device is within a self refresh mode.

公开(公告)号：US10997096B2

公开(公告)日：2021-05-04

申请号：US15987854

申请日：2018-05-23

申请人： Intel Corporation

发明人： Tonia G. Morris ,  Bill Nale

IPC分类号： G06F13/16 ,  G06F3/06 ,  G06F9/30 ,  G06F12/02 ,  G06F1/26

摘要： A memory subsystem enables per device addressability (PDA) to target configuration commands to one of multiple memory devices that share a select line or buffer devices that share an enable line. The system includes a host and multiple memory devices that can be coupled over a command bus and a data bus. The devices include a configuration or mode register to store a value to indicate whether PDA enumeration is enabled. When enabled, the host can provide an enumeration identifier (ID) command via the command bus with a signal via the data bus to assign an enumeration ID. After assignment of the enumeration ID, the host can send PDA commands via the command bus with the enumeration ID, without a signal on the data bus. Devices only process PDA commands that match their assigned enumeration ID, enabling the setting of device-specific configuration settings without needing to use the data bus on every PDA command.

公开(公告)号：US10795755B2

公开(公告)日：2020-10-06

申请号：US15080577

申请日：2016-03-24

申请人： INTEL CORPORATION

发明人： Bill Nale ,  Jonathan C. Jasper ,  Murugasamy K. Nachimuthu ,  Jun Zhu ,  Tuan M. Quach

IPC分类号： G06F12/00 ,  G06F11/07 ,  G11C29/02 ,  G06F12/0813 ,  G06F13/16 ,  G06F3/06 ,  G06F12/0802 ,  G06F12/02 ,  G06F13/42 ,  G11C7/10 ,  G11C7/22 ,  G11C11/406 ,  G11C5/14 ,  H04L9/08 ,  G11C5/04

摘要： Provided are a method and apparatus for performing error handling operations using error signals A first error signal is asserted on an error pin on a bus to signal to a host memory controller that error handling operations are being performed by a memory module controller in response to detecting an error. Error handling operations are performed to return the bus to an initial state in response to detecting the error. A second error signal is asserted on the error pin on the bus to signal that error handling operations have completed and the bus is returned to the initial state.

公开(公告)号：US10339072B2

公开(公告)日：2019-07-02

申请号：US15089455

申请日：2016-04-01

申请人： Intel Corporation

发明人： Bill Nale ,  Pete D Vogt

IPC分类号： G06F13/16 ,  G06F3/06 ,  G06F13/40 ,  G11C5/06 ,  G11C7/10 ,  G11C5/04

摘要： A system with memory includes a repeater architecture where the memory connects to a host with one bandwidth, and a repeater extends a channel with a lower bandwidth. A memory circuit includes a first group of memory devices coupled point-to-point to a host device via a first group of read signal lines. The memory circuit includes a second group of memory devices coupled point-to-point to the first group of memory devices second group of read signal lines to extend the memory channel to the second group of memory devices. The second group of read signal lines has fewer read signal lines than the first group. The memory circuit includes a repeater to share read bandwidth between the first and second groups of memory devices, with up to a portion of the bandwidth for reads to the second group of memory devices, and at least an amount equal to the bandwidth less the portion for reads to the first group of memory devices. The repeater or buffer may accumulate data read from the second group of memory devices or a second memory module and burst the accumulated data to the host device with the first bandwidth.

公开(公告)号：US09904591B2

公开(公告)日：2018-02-27

申请号：US14918428

申请日：2015-10-20

申请人： Intel Corporation

发明人： John B. Halbert ,  Kuljit S. Bains ,  Debaleena Das ,  Bill Nale

IPC分类号： G11C29/00 ,  G06F11/10 ,  G06F11/07 ,  G06F13/00 ,  G06F11/08

CPC分类号： G06F11/1004 ,  G06F11/073 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/08 ,  G06F13/00

摘要： Techniques and mechanisms to provide selective access to data error information by a memory controller. In an embodiment, a memory device stores a first value representing a baseline number of data errors determined prior to operation of the memory device with the memory controller. Error detection logic of the memory device determines a current count of data errors, and calculates a second value representing a difference between the count of data errors and the baseline number of data errors. The memory device provides the second value to the memory controller, which is unable to identify that the second value is a relative error count. In another embodiment, the memory controller is restricted from retrieving the baseline number of data errors.

公开(公告)号：US09811420B2

公开(公告)日：2017-11-07

申请号：US14670413

申请日：2015-03-27

申请人： Intel Corporation

发明人： Debaleena Das ,  Bill Nale ,  Kuljit S Bains ,  John B Halbert

IPC分类号： G06F11/00 ,  G06F11/10

CPC分类号： G06F11/1048 ,  G06F11/00 ,  G06F11/1008 ,  G06F11/1076 ,  G06F11/1084

摘要： Error correction in a memory subsystem includes a memory device generating internal check bits after performing internal error detection and correction, and providing the internal check bits to the memory controller. The memory device performs internal error detection to detect errors in read data in response to a read request from the memory controller. The memory device selectively performs internal error correction if an error is detected in the read data. The memory device generates check bits indicating an error vector for the read data after performing internal error detection and correction, and provides the check bits with the read data to the memory controller in response to the read request. The memory controller can apply the check bits for error correction external to the memory device.

公开(公告)号：US09632862B2

公开(公告)日：2017-04-25

申请号：US14578413

申请日：2014-12-20

申请人： Intel Corporation

发明人： Brian S. Morris ,  Bill Nale ,  Robert G. Blankenship ,  Eric L. Hendrickson

IPC分类号： G06F11/00 ,  G06F11/08 ,  G06F11/16 ,  G06F13/00 ,  H04L1/00 ,  H04L1/18

CPC分类号： G06F11/08 ,  G06F11/1625 ,  G06F11/1654 ,  G06F11/167 ,  G06F13/00 ,  H04L1/00 ,  H04L1/0061 ,  H04L1/0082 ,  H04L1/1838 ,  H04L2001/0097

摘要： Data is sent from a memory buffer device to a host device over a link. An error in the data is determined. A read response cancellation signal is sent to the host device to indicate the error to the host device, where the read response cancellation signal is to be sent subsequent to the data being sent from the memory buffer device to the host device.

公开(公告)号：US20160188500A1

公开(公告)日：2016-06-30

申请号：US14583147

申请日：2014-12-25

申请人： Intel Corporation

发明人： Brian S. Morris ,  Jeffrey C. Swanson ,  Bill Nale ,  Robert G. Blankenship ,  Jeff Willey ,  Eric L. Hendrickson

IPC分类号： G06F13/16 ,  G11C7/10

CPC分类号： G06F13/1663 ,  G06F13/1673 ,  G11C5/04 ,  G11C7/10

摘要： A plurality of completed writes to memory are identified corresponding to a plurality of write requests from a host device received over a buffered memory interface. A completion packet is sent to the host device that includes a plurality of write completions to correspond to the plurality of completed writes.

摘要翻译： 对存储器的多个完成的写入被识别为与通过缓冲存储器接口接收的主机设备的多个写入请求相对应。 完成分组被发送到主机设备，其包括多个写入完成以对应于多个完成的写入。