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公开(公告)号：US09767037B2
公开(公告)日：2017-09-19
申请号：US14751454
申请日：2015-06-26
Applicant: Intel Corporation
Inventor： Marcelo S. Cintra , Cheng Wang , Youfeng Wu , Alexandre Xavier DuChateau
IPC: G06F12/10 , G06F12/02 , G06F12/1009
CPC classification number: G06F12/1009 , G06F8/447 , G06F9/3836 , G06F9/44568 , G06F12/0238 , G06F12/0292 , G06F2212/1044
Abstract: Technologies for persistent memory pointer access include a computing device having a persistent memory including one or more nonvolatile regions. The computing device may load a persistent memory pointer having a static region identifier, a segment identifier, and an offset from the persistent memory. The computing device may map the static region identifier to a dynamic region identifier and determine a virtual memory address of the persistent memory pointer target based on the dynamic region identifier, the segment identifier, and the offset. The computing device may load an in-storage representation of a persistent-export pointer from the persistent memory, map the in-storage representation to a runtime representation, and determine a target address of a persistent external data object based on the runtime representation. The computing device may include a compiler to generate output code including persistent memory pointer and/or persistent-export pointer accesses. Other embodiments are described and claimed.
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公开(公告)号：US09690552B2
公开(公告)日：2017-06-27
申请号：US14583657
申请日：2014-12-27
Applicant: Intel Corporation
Inventor： Hongbo Rong , Peng Tu , Tatiana Shpeisman , Hai Liu , Todd A. Anderson , Youfeng Wu , Paul M. Petersen , Victor W. Lee , P. G. Lowney , Arch D. Robison , Cheng Wang
CPC classification number: G06F8/43 , G06F8/31 , G06F8/443 , G06F8/4441 , G06F8/453 , G06F8/49 , G06F8/54
Abstract: Technologies for generating composable library functions include a first computing device that includes a library compiler configured to compile a composable library and second computing device that includes an application compiler configured to compose library functions of the composable library based on a plurality of abstractions written at different levels of abstractions. For example, the abstractions may include an algorithm abstraction at a high level, a blocked-algorithm abstraction at medium level, and a region-based code abstraction at a low level. Other embodiments are described and claimed herein.
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公开(公告)号：US09588814B2
公开(公告)日：2017-03-07
申请号：US14582430
申请日：2014-12-24
Applicant: INTEL CORPORATION
Inventor： Sara S. Baghsorkhi , Albert Hartono , Youfeng Wu , Cheng Wang
CPC classification number: G06F9/50 , G06F9/30 , G06F9/3834 , G06F9/3838
Abstract: The present disclosure is directed to fast approximate conflict detection. A device may comprise, for example, a memory, a processor and a fast conflict detection module (FCDM) to cause the processor to perform fast conflict detection. The FCDM may cause the processor to read a first and second vector from memory, and to then generate summaries based on the first and second vectors. The summaries may be, for example, shortened versions of write and read addresses in the first and second vectors. The FCDM may then cause the processor to distribute the summaries into first and second summary vectors, and may then determine potential conflicts between the first and second vectors by comparing the first and second summary vectors. The summaries may be distributed into the first and second summary vectors in a manner allowing all of the summaries to be compared to each other in one vector comparison transaction.
Abstract translation: 本公开涉及快速近似冲突检测。 设备可以包括例如存储器，处理器和快速冲突检测模块（FCDM），以使处理器执行快速冲突检测。 FCDM可以使处理器从存储器读取第一和第二矢量，然后基于第一和第二矢量生成汇总。 摘要可以是例如第一和第二向量中的写入和读取地址的缩写版本。 然后，FCDM可以使处理器将摘要分发到第一和第二摘要向量中，然后可以通过比较第一和第二概括向量来确定第一和第二向量之间的潜在冲突。 总结可以以允许在一个向量比较事务中将所有概要相互比较的方式分发到第一和第二摘要向量中。
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公开(公告)号：US09542211B2
公开(公告)日：2017-01-10
申请号：US14225755
申请日：2014-03-26
Applicant: Intel Corporation
Inventor： Cheng Wang , Youfeng Wu , Hongbo Rong , Hyunchul Park
CPC classification number: G06F9/45516 , G06F9/4411 , G06F9/4552 , G06F13/10
Abstract: In an embodiment, a processor includes at least one core and a dynamic language accelerator to execute a bytecode responsive to a memory mapped input/output (MMIO) operation on a file descriptor associated with the dynamic language accelerator. The processor may block execution of native code while the dynamic language accelerator executes the bytecode. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，处理器包括至少一个核心和动态语言加速器，以响应于与动态语言加速器相关联的文件描述符的存储器映射的输入/输出（MMIO）操作来执行字节码。 当动态语言加速器执行字节码时，处理器可能会阻止本地代码的执行。 描述和要求保护其他实施例。
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25.发明申请公开(公告)号：US20160019038A1
公开(公告)日：2016-01-21
申请号：US14867950
申请日：2015-09-28
Applicant: Intel Corporation
Inventor： Mauricio Breternitz, JR. , Youfeng Wu , Cheng Wang , Edson Borin , Shiliang Hu , Criag B. Zilles
CPC classification number: G06F8/443 , G06F8/52 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/30116 , G06F9/3842 , G06F9/3857 , G06F9/466 , G06F11/3672 , G06F11/3688
Abstract: An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.
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Patent Agency Ranking
公开(公告)号：US10437319B2
公开(公告)日：2019-10-08
申请号：US14986678
申请日：2016-01-02
Applicant: Intel Corporation
Inventor： Youfeng Wu , Shiliang Hu , Edson Borin , Cheng Wang
Abstract: Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.
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公开(公告)号：US10324768B2
公开(公告)日：2019-06-18
申请号：US14574300
申请日：2014-12-17
Applicant: Intel Corporation
Inventor： Cheng Wang , Youfeng Wu , Sara S. Baghsorkhi , Albert Hartono , Robert Valentine
IPC: G06F9/30 , G06F9/52 , G06F12/0875 , G06F12/0817
Abstract: Embodiments described herein utilize restricted transactional memory (RTM) instructions to implement speculative compile time optimizations that will be automatically rolled back by hardware in the event of a missed speculation. In one embodiment, a lightweight version of RTM for speculative compiler optimization is described to provide lower operational overhead in comparison to conventional RTM implementations used when performing SLE.
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28.发明授权公开(公告)号：US09817644B2
公开(公告)日：2017-11-14
申请号：US14867950
申请日：2015-09-28
Applicant: Intel Corporation
Inventor： Mauricio Breternitz, Jr. , Youfeng Wu , Cheng Wang , Edson Borin , Shiliang Hu , Craig B. Zilles
CPC classification number: G06F8/443 , G06F8/52 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/30116 , G06F9/3842 , G06F9/3857 , G06F9/466 , G06F11/3672 , G06F11/3688
Abstract: An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.
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公开(公告)号：US20160378679A1
公开(公告)日：2016-12-29
申请号：US14751454
申请日：2015-06-26
Applicant: Intel Corporation
Inventor： Marcelo S. Cintra , Cheng Wang , Youfeng Wu , Alexandre Xavier DuChateau
CPC classification number: G06F12/1009 , G06F8/447 , G06F9/3836 , G06F9/44568 , G06F12/0238 , G06F12/0292 , G06F2212/1044
Abstract: Technologies for persistent memory pointer access include a computing device having a persistent memory including one or more nonvolatile regions. The computing device may load a persistent memory pointer having a static region identifier, a segment identifier, and an offset from the persistent memory. The computing device may map the static region identifier to a dynamic region identifier and determine a virtual memory address of the persistent memory pointer target based on the dynamic region identifier, the segment identifier, and the offset. The computing device may load an in-storage representation of a persistent-export pointer from the persistent memory, map the in-storage representation to a runtime representation, and determine a target address of a persistent external data object based on the runtime representation. The computing device may include a compiler to generate output code including persistent memory pointer and/or persistent-export pointer accesses. Other embodiments are described and claimed.
Abstract translation: 用于持久存储器指针访问的技术包括具有包括一个或多个非易失性区域的持久存储器的计算设备。 计算设备可以从永久存储器加载具有静态区域标识符，段标识符和偏移的持久存储器指针。 计算设备可以将静态区域标识符映射到动态区域标识符，并且基于动态区域标识符，段标识符和偏移来确定持久存储器指针目标的虚拟存储器地址。 计算设备可以从永久存储器加载持久输出指针的存储器表示，将存储器表示映射到运行时表示，并且基于运行时表示来确定持久外部数据对象的目标地址。 计算设备可以包括用于生成包括持久存储器指针和/或持久输出指针访问的输出代码的编译器。 描述和要求保护其他实施例。
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公开(公告)号：US20140223166A1
公开(公告)日：2014-08-07
申请号：US14169955
申请日：2014-01-31
Applicant: INTEL CORPORATION
Inventor： Youfeng Wu , Shiliang Hu , Edson Borin , Cheng Wang
IPC: G06F9/445
CPC classification number: G06F1/329 , G06F1/3287 , G06F9/3851 , G06F9/445 , G06F9/4893 , G06F9/5027 , G06F9/5094 , G06F11/3409 , G06F11/3452 , G06F11/3466 , G06F2201/81 , G06F2201/865 , G06F2201/88 , G06F2209/501 , Y02D10/171 , Y02D10/22 , Y02D10/34 , Y02D50/20
Abstract: Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.
Abstract translation: 可以通过在第一处理核上执行程序代码来执行异构多核处理系统上的动态切换核。 可以用信号通知第二处理核心的加电。 可以收集执行程序代码的第一处理核心的第一性能度量。 当第一性能指标优于先前确定的核心性能指标时，可以发信号通知第二处理核心的掉电，并且可以在第一处理核心上继续执行程序代码。 当第一性能度量不比先前确定的核心性能指标更好时，程序代码的执行可以从第一处理核心切换到第二处理核心。
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