公开(公告)号：US20170177065A1

公开(公告)日：2017-06-22

申请号：US14971302

申请日：2015-12-16

Applicant: Intel Corporation

Inventor： Doron Rajwan ,  Dorit Shapira ,  Itai Feit ,  Nadav Shulman ,  Efraim (Efi) Rotem ,  Tal Kuzi ,  Eliezer Weissmann ,  Tomer Ziv ,  Nir Rosenzweig

IPC: G06F1/32 ,  G06F13/42

Abstract: A method and apparatus for providing power state information using in-band signaling are described. In one embodiment, an integrated circuit (IC) device comprises a controller operable to receive a command from a platform control bus, the command requesting data that is unrelated to information about a power state in which the IC resides; and control logic operable to obtain data for inclusion in a response to the command, wherein the controller is operable to send the response over a bus, the response containing at least a portion of the data responsive to the command and containing power state information for the IC.

公开(公告)号：US11567556B2

公开(公告)日：2023-01-31

申请号：US16833008

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Chris Macnamara ,  John J. Browne ,  Tomasz Kantecki ,  David Hunt ,  Anatoly Burakov ,  Srihari Makineni ,  Nikhil Gupta ,  Ankush Varma ,  Dorit Shapira ,  Vasudevan Srinivasan ,  Bryan T. Butters ,  Shrikant M. Shah

IPC: G06F1/324 ,  G06F1/20 ,  G06F9/50 ,  G06F1/3296

Abstract: Examples herein relate to assigning, by a system agent of a central processing unit (CPU), an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent. Avoiding throttling of the system agent can include maintaining a minimum performance level of the system agent. A minimum performance level of the system agent can be based on a minimum operating frequency. Assigning, by a system agent of a central processing unit, an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent can avoid a thermal limit of the CPU. Avoiding thermal limit of the CPU can include adjusting the operating frequency to the core group to avoid performance indicators of the CPU. A performance indicator can indicate CPU utilization corresponds to Thermal Design Point (TDP).

公开(公告)号：US11054877B2

公开(公告)日：2021-07-06

申请号：US16012623

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Dorit Shapira ,  Anand K. Enamandram ,  Daniel Cartagena ,  Krishnakanth Sistla ,  Jorge P. Rodriguez ,  Efraim Rotem ,  Nir Rosenzweig

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3296 ,  G06F1/324 ,  G06F1/3234 ,  H03M1/12

Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first sensing system to measure first power consumed by first one or more components of the plurality of components; a second sensing system to measure second power consumed by the apparatus; an analog-to-digital converter (ADC) to generate an identification (ID) that is representative of the second power consumed by the apparatus; and a controller to allocate power budget to one or more components of the plurality of components, based on the measurement of the first power and the ID.

公开(公告)号：US10678319B2

公开(公告)日：2020-06-09

申请号：US16252012

申请日：2019-01-18

Applicant: Intel Corporation

Inventor： Doron Rajwan ,  Efraim Rotem ,  Eliezer Weissmann ,  Avinash N. Ananthakrishnan ,  Dorit Shapira

IPC: G06F1/32 ,  G06F15/76 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3237 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3293 ,  G06F30/34 ,  G06F119/06 ,  G06F119/08

Abstract: In an embodiment, a processor includes processing cores, and a central control unit to: concurrently execute an outer control loop and an inner control loop, wherein the outer control loop is to monitor the processor as a whole, and wherein the inner control loop is to monitor a first processing core included in the processor; determine, based on the outer control loop, a first control action for the first processing core included in the processor; determine, based on the inner control loop, a second control action for the first processing core included in the processor; based on a comparison of the first control action and the second control action, select one of the first control action and the second control action as a selected control action; and apply the selected control action to the first processing core. Other embodiments are described and claimed.

公开(公告)号：US10474216B2

公开(公告)日：2019-11-12

申请号：US14971302

申请日：2015-12-16

Applicant: Intel Corporation

Inventor： Doron Rajwan ,  Dorit Shapira ,  Itai Feit ,  Nadav Shulman ,  Efraim (Efi) Rotem ,  Tal Kuzi ,  Eliezer Weissmann ,  Tomer Ziv ,  Nir Rosenzweig

IPC: G06F1/32 ,  G06F13/42 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3296

Abstract: A method and apparatus for providing power state information using in-band signaling are described. In one embodiment, an integrated circuit (IC) device comprises a controller operable to receive a command from a platform control bus, the command requesting data that is unrelated to information about a power state in which the IC resides; and control logic operable to obtain data for inclusion in a response to the command, wherein the controller is operable to send the response over a bus, the response containing at least a portion of the data responsive to the command and containing power state information for the IC.

公开(公告)号：US20180373287A1

公开(公告)日：2018-12-27

申请号：US15632000

申请日：2017-06-23

Applicant: Intel Corporation

Inventor： Asma H. Al-Rawi ,  Federico Ardanaz ,  Jonathan M. Eastep ,  Dorit Shapira ,  Krishnakanth Sistla ,  Nikhil Gupta ,  Vasudevan Srinivasan ,  Chris MacNamara

IPC: G06F1/06 ,  G06F1/04 ,  G06F1/08 ,  G06F9/50

Abstract: An apparatus system is provided which comprises: a first component and a second component; a first circuitry to assign the first component to a first group of components, and to assign the second component to a second group of components; and a second circuitry to assign a first maximum frequency limit to the first group of components, and to assign a second maximum frequency limit to the second group of components, wherein the first component and the second component are to respectively operate in accordance with the first maximum frequency limit and the second maximum frequency limit.

公开(公告)号：US20180059748A1

公开(公告)日：2018-03-01

申请号：US15702970

申请日：2017-09-13

Applicant: Intel Corporation

Inventor： Nir Rosenzweig ,  Doron Rajwan ,  Dorit Shapira ,  Nadav Shulman ,  Tomer Ziv

IPC: G06F1/20 ,  G06F1/32 ,  G01K13/00

CPC classification number: G06F1/206 ,  G01K1/026 ,  G01K13/00 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/324 ,  G06F9/5094

Abstract: In an embodiment, a processor includes a plurality of cores and a plurality of temperature sensors, where each core is proximate to at least one temperature sensor. The processor also includes a power control unit (PCU) including temperature logic to receive temperature data that includes a corresponding temperature value from each of the temperature sensors. Responsive to an indication that a highest temperature value of the temperature data exceeds a threshold, the temperature logic is to adjust a plurality of domain frequencies according to a determined policy that is based on instruction execution characteristics of at least two of the plurality of cores. Each domain frequency is associated with a corresponding domain that includes at least one of the plurality of cores and each domain frequency is independently adjustable. Other embodiments are described and claimed.

公开(公告)号：US09535812B2

公开(公告)日：2017-01-03

申请号：US13930212

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： Doron Rajwan ,  Nadav Shulman ,  Dorit Shapira ,  Kosta Luria ,  Efraim Rotem

IPC: G06F11/00 ,  G06F11/30 ,  G06F11/34

CPC classification number: G06F11/3037 ,  G06F11/3419 ,  G06F11/3476 ,  G06F2201/88

Abstract: In an embodiment, a processor includes measurement logic to measure a usage associated with the processor. The processor also includes statistical logic to determine, based on a statistical procedure, whether to provide a permission to record an increase in usage responsive to an indication that the usage has increased by a defined amount. The processor also includes control logic to record the defined increase in usage in non-volatile memory responsive to receipt of the permission to record from the statistical logic. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括用于测量与处理器相关联的使用的测量逻辑。 处理器还包括用于基于统计过程来确定是否提供响应于使用已经增加了定义量的指示来记录使用增加的许可的统计逻辑。 处理器还包括控制逻辑，用于响应于从统计逻辑接收到记录的许可而记录在非易失性存储器中的定义的使用增加。 描述和要求保护其他实施例。