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公开(公告)号：US11038749B2
公开(公告)日：2021-06-15
申请号：US16231807
申请日：2018-12-24
Applicant: INTEL CORPORATION
Inventor： Ang Li , Eng Hun Ooi , Kuan Hua Tan
Abstract: A handshake communication mechanism between a host and an end-point device permits multiple Base Address Registers (BAR registers) to be configured to size or resize the mapped address spaces associated with each BAR register. In one embodiment, the handshake communication mechanism includes a single address space reconfiguration request which may be transmitted in a single transaction layer packet, to request the configuration of multiple BAR registers of an end-point device. Other features and advantages may be realized, depending upon the particular application.
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公开(公告)号：US10977197B2
公开(公告)日：2021-04-13
申请号：US16367846
申请日：2019-03-28
Applicant: Intel Corporation
Inventor： Kuan Hua Tan , Ang Li , Eng Hun Ooi
IPC: G06F1/26 , G06F1/32 , G06F13/16 , G06F1/3234 , G06F9/30 , G06F9/50 , G06F1/3206
Abstract: Systems and devices can include a power management controller to determine a low power mode exit timing from a plurality of low power mode exit timing options, and cause the setting of a low power mode control register based on the determined low power mode exit timing. A message generator can generate a power mode request message. The power mode request message indicating the determined low power mode exiting timing. The power mode request message can be transmitted to a host across a multilane link.
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23.发明申请公开(公告)号：US20200212943A1
公开(公告)日：2020-07-02
申请号：US16639780
申请日：2018-09-17
Applicant: Intel Corporation
Inventor： Elan Banin , Eytan Mann , Rotem Banin , Ronen Gernizky , Ofir Degani , Igal Kushnir , Shahar Porat , Amir Rubin , Vladimir Volokitin , Elinor Kashani , Dmitry Felsenstein , Ayal Eshkoli , Tal Davidson , Eng Hun Ooi , Yossi Tsfati , Ran Shimon
Abstract: An apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.
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公开(公告)号：US10649484B2
公开(公告)日：2020-05-12
申请号：US15960074
申请日：2018-04-23
Applicant: INTEL CORPORATION
Inventor： Anoop Mukker , Eng Hun Ooi , Robert J. Royer, Jr. , Brian R. McFarlane
Abstract: The present disclosure provides devices and techniques to dynamically change the operating frequency of an interface where components on the interface have non-common clocks. An interface component may be provided with a frequency negotiation component to negotiate a shift in an operating frequency with other component on an interface where the different components have non-common clocks.
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公开(公告)号：US20190129792A1
公开(公告)日：2019-05-02
申请号：US15756039
申请日：2018-02-27
Applicant: Intel Corporation
Inventor： Robert J. Royer, JR. , Blaise Fanning , Eng Hun Ooi
IPC: G06F11/10 , G06F12/0866
CPC classification number: G06F11/1064 , G06F11/1048 , G06F12/084 , G06F12/0866 , G06F2212/1032 , G06F2212/313
Abstract: Apparatus, systems, and methods to manage memory latency operations are described. In one embodiment, an electronic device comprises a processor and a memory control logic to receive data from a remote memory device, store the data in a local cache memory, receive an error correction code indicator associated with the data, and implement a data management policy in response to the error correction code indicator. Other embodiments are also disclosed and claimed.
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Patent Agency Ranking
公开(公告)号：US09910771B2
公开(公告)日：2018-03-06
申请号：US15396732
申请日：2017-01-02
Applicant: Intel Corporation
Inventor： Eng Hun Ooi , Robert J. Royer, Jr. , Michael W. Williams , Jeffrey R. Wilcox , Ritesh B. Trivedi , Blaise Fanning
CPC classification number: G06F12/0246 , G06F3/0679 , G06F12/02 , G06F13/12 , G06F13/16 , G06F13/1668 , G06F13/38 , G06F13/4234 , G06F2212/7202
Abstract: In an embodiment, a memory interface may send an indication that a request is being sent. The indication may be sent to a non-volatile memory via a point-to-point bus between a memory interface and the non-volatile memory. The memory interface may send the request to the non-volatile memory via the bus. The request may include an address that may be used to identify a location for storing or reading data. The non-volatile memory may acquire the request from the bus and process the request. After processing the request, the non-volatile memory may send an indication to the memory interface that indicates the non-volatile memory has a response to send to the memory interface. The memory interface may grant access to the bus to the non-volatile memory. After being granted access to the bus, the non-volatile memory may send the response to the memory interface.
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公开(公告)号：US09594910B2
公开(公告)日：2017-03-14
申请号：US14229708
申请日：2014-03-28
Applicant: Intel Corporation
Inventor： Nitin V. Sarangdhar , Robert J. Royer, Jr. , Eng Hun Ooi , Brian R. McFarlane , Mukesh Kataria
CPC classification number: G06F21/572 , G06F9/4403 , G06F9/4406 , G06F9/4411 , G06F11/1417 , G06F21/57 , G06F21/575 , G06F2212/1052 , G06F2221/03 , G06F2221/033
Abstract: A hardware platform includes a nonvolatile storage device that can store system firmware as well as code for the primary operating system for the hardware platform. The hardware platform includes a controller that determines the hardware platform lacks functional firmware to boot the primary operating system from the storage device. The controller accesses a firmware image from an external interface that interfaces a device external to the hardware platform, where the external device is a firmware image source. The controller provisions the firmware from the external device to the storage device and initiates a boot sequence from the provisioned firmware.
Abstract translation: 硬件平台包括可以存储系统固件的非易失性存储设备以及用于硬件平台的主操作系统的代码。 硬件平台包括一个确定硬件平台的控制器缺乏从存储设备引导主操作系统的功能固件。 控制器从外部接口访问固件映像，该外部接口将硬件平台外部的设备连接到外部设备是固件映像源。 控制器将固件从外部设备提供给存储设备，并从配置的固件启动启动顺序。
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公开(公告)号：US09535829B2
公开(公告)日：2017-01-03
申请号：US14128669
申请日：2013-07-26
Applicant: Intel Corporation
Inventor： Eng Hun Ooi , Robert J. Royer, Jr. , Michael W. Williams , Jeffrey R. Wilcox , Ritesh B. Trivedi , Blaise Fanning
CPC classification number: G06F12/0246 , G06F3/0679 , G06F12/02 , G06F13/12 , G06F13/16 , G06F13/1668 , G06F13/38 , G06F13/4234 , G06F2212/7202
Abstract: In an embodiment, a memory interface may send an indication that a request is being sent. The indication may be sent to a non-volatile memory via a point-to-point bus between a memory interface and the non-volatile memory. The memory interface may send the request to the non-volatile memory via the bus. The request may include an address that may be used to identify a location for storing or reading data. The non-volatile memory may acquire the request from the bus and process the request. After processing the request, the non-volatile memory may send an indication to the memory interface that indicates the non-volatile memory has a response to send to the memory interface. The memory interface may grant access to the bus to the non-volatile memory. After being granted access to the bus, the non-volatile memory may send the response to the memory interface.
Abstract translation: 在一个实施例中，存储器接口可以发送请求被发送的指示。 该指示可以经由存储器接口和非易失性存储器之间的点对点总线发送到非易失性存储器。 存储器接口可以经由总线将请求发送到非易失性存储器。 请求可以包括可用于标识用于存储或读取数据的位置的地址。 非易失性存储器可以从总线获取请求并处理请求。 在处理请求之后，非易失性存储器可以向存储器接口发送指示非易失性存储器具有发送到存储器接口的响应的指示。 存储器接口可以向总线授予对非易失性存储器的访问。 在被允许访问总线之后，非易失性存储器可以将响应发送到存储器接口。
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公开(公告)号：US20160188523A1
公开(公告)日：2016-06-30
申请号：US14583623
申请日：2014-12-27
Applicant: Intel Corporation
Inventor： Ee Loon Teoh , Eng Hun Ooi , Christopher P. Mozak , Brian R. McFarlane
CPC classification number: G06F13/4282 , G06F13/1668 , G06F13/28 , G06F21/79 , Y02D10/14 , Y02D10/151
Abstract: An I/O interface supports scrambling, where the scrambling can include nonlinear scrambling of the scrambling code, or dynamic bus inversion of the scrambling code, or selective switching of selected bits of the scrambling code, or a combination of these. The transmitting device includes a scrambler and the receiving device includes a descrambler. Both the scrambler and the descrambler generate a linear feedback scrambling code modified by applying one or more of the techniques mentioned above. The modified scrambling code may cause fewer than half of the scrambled output bits to be toggled with respect to a previous scrambled output. The scrambler applies the modified scrambling code to a signal to transmit. The descrambler applies the modified scrambling code to a received signal.
Abstract translation: I / O接口支持加扰，其中加扰可以包括扰码的非线性加扰或扰码的动态总线反转，或扰码的选定位的选择性切换，或这些的组合。 发送设备包括加扰器，并且接收设备包括解扰器。 加扰器和解扰器都产生通过应用上述一种或多种技术修改的线性反馈扰码。 经修改的扰码可能导致少于一半的加扰输出比特相对于先前的加扰输出被切换。 扰频器将修改的扰码应用于要发送的信号。 解扰器将修改的扰码应用于接收信号。
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公开(公告)号：US20210357350A1
公开(公告)日：2021-11-18
申请号：US17387261
申请日：2021-07-28
Applicant: Intel Corporation
Inventor： Kuan Hua Tan , Eng Hun Ooi , Ang Li
Abstract: A device connected by a link to a host system can include a first port to receive a capability configuration message across a link and a message request receiving logic comprising hardware circuitry to identify a capability of the device identified in the capability configuration message, determine that the capability is to be presented or hidden from operation based on a capability hide enable bit in the capability configuration message, and configure a capability linked list to present or hide the capability based on the determination. The device can also include a message response generator logic comprising hardware circuitry to generate a response message indicating that the capability is to be presented or hidden from operation. The device can include a second port to transmit the response message across the link.
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