公开(公告)号：US20220406778A1

公开(公告)日：2022-12-22

申请号：US17353263

申请日：2021-06-21

Applicant: Intel Corporation

Inventor： Tahir GHANI ,  Biswajeet GUHA ,  Mohit K. HARAN ,  Mohammad HASAN ,  Reken PATEL ,  Sean PURSEL ,  Jake JAFFE

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

Abstract: Integrated circuit structures having plugged metal gates, and methods of fabricating integrated circuit structures having plugged metal gates, are described. For example, an integrated circuit structure includes a fin having a portion protruding above a shallow trench isolation (STI) structure. A gate dielectric material layer is over the protruding portion of the fin and over the STI structure. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin, the dielectric gate plug on the STI structure. The gate dielectric material layer and the conductive gate layer are along a side of the dielectric gate plug, and the gate dielectric material layer is in direct contact with an entirety of the side of the dielectric gate plug.

公开(公告)号：US20220399335A1

公开(公告)日：2022-12-15

申请号：US17347024

申请日：2021-06-14

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Mohammad HASAN ,  Charles H. WALLACE ,  Tahir GHANI

IPC: H01L27/092 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06

Abstract: Integrated circuit structures having backside gate partial cut or backside trench contact partial cut and/or spit epitaxial structure are described. For example, an integrated circuit structure includes a first sub-fin structure over a first stack of nanowires. A second sub-fin structure is over a second stack of nanowires. A first portion of a gate electrode is around the first stack of nanowires, a second portion of the gate electrode is around the second stack of nanowires, and a third portion of the gate electrode bridges the first and second portions of the gate electrode. A dielectric structure is between the first portion of the gate electrode and the second portion of the gate electrode, the dielectric structure over the third portion of the gate electrode. The dielectric structure is continuous along the first and second portions of the gate electrode and the first and second sub-fin structures.

公开(公告)号：US20240178226A1

公开(公告)日：2024-05-30

申请号：US18437961

申请日：2024-02-09

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Michael K. HARPER ,  William HSU ,  Biswajeet GUHA ,  Tahir GHANI ,  Niels ZUSSBLATT ,  Jeffrey Miles TAN ,  Benjamin KRIEGEL ,  Mohit K. HARAN ,  Reken PATEL ,  Oleg GOLONZKA ,  Mohammad HASAN

IPC: H01L27/088 ,  G11C5/06 ,  H01L27/06 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  G11C5/06 ,  H01L27/0688 ,  H01L29/0669 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Gate-all-around integrated circuit structures having pre-spacer-deposition cut gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. The integrated circuit structure also includes a dielectric structure having a first portion forming a gate spacer along sidewalls of the first gate stack, a second portion forming a gate spacer along sidewalls of the second gate stack, and a third portion completely filling the gap, the third portion continuous with the first and second portions.

公开(公告)号：US20240154037A1

公开(公告)日：2024-05-09

申请号：US18400772

申请日：2023-12-29

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Tahir GHANI ,  Charles H. WALLACE ,  Mohit K. HARAN ,  Mohammad HASAN ,  Aryan NAVABI-SHIRAZI ,  Allen B. GARDINER

IPC: H01L29/786 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/78618 ,  H01L21/823418 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/785 ,  H01L29/0673

Abstract: Integrated circuit structures having a dielectric anchor and confined epitaxial source or drain structure, and methods of fabricating integrated circuit structures having a dielectric anchor and confined epitaxial source or drain structure, are described. For example, an integrated circuit structure includes a sub-fin in a shallow trench isolation (STI) structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is surrounding the plurality of horizontally stacked nanowires. A gate electrode structure is over the gate dielectric material layer. A confined epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A dielectric anchor is laterally spaced apart from the plurality of horizontally stacked nanowires and recessed into a first portion of the STI structure, the dielectric anchor having an uppermost surface below an uppermost surface of the confined epitaxial source or drain structure.

公开(公告)号：US20220399445A1

公开(公告)日：2022-12-15

申请号：US17347034

申请日：2021-06-14

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Tahir GHANI ,  Charles H. WALLACE ,  Conor P. PULS ,  Walid M. HAFEZ ,  Sairam SUBRAMANIAN ,  Justin S. SANDFORD ,  Saurabh MORARKA ,  Sean PURSEL ,  Mohammad HASAN

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/423 ,  H01L29/06 ,  H01L21/8234

Abstract: Conductive via bars self-aligned to gate ends are described. In an example, an integrated circuit structure includes a plurality of gate structures. The integrated circuit structure also includes a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers laterally surrounding a corresponding one of the plurality of gate structures. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. A conductive via bar is along ends of the plurality of gate structures and ends of the plurality of conductive trench contact structures, wherein the plurality of dielectric spacers is between the ends of the plurality of gate structures and the conductive via bar.

公开(公告)号：US20220399333A1

公开(公告)日：2022-12-15

申请号：US17346990

申请日：2021-06-14

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Biswajeet GUHA ,  Tahir GHANI ,  Mohit K. HARAN ,  Mohammad HASAN

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78

Abstract: Integrated circuit structures having metal gates with reduced aspect ratio cuts, and methods of fabricating integrated circuit structures having metal gates with reduced aspect ratio cuts, are described. For example, an integrated circuit structure includes a sub-fin having a portion protruding above a shallow trench isolation (STI) structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is over the protruding portion of the sub-fin, over the STI structure, and surrounding the horizontally stacked nanowires. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric structure is laterally spaced apart from the plurality of horizontally stacked nanowires. A dielectric gate plug is landed on the dielectric structure.

公开(公告)号：US20220392808A1

公开(公告)日：2022-12-08

申请号：US17339160

申请日：2021-06-04

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Mohammad HASAN ,  William HSU ,  Biswajeet GUHA ,  Charles H. WALLACE ,  Tahir GHANI ,  Sean PURSEL ,  Tsuan-Chung CHANG

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: Gate aligned fin cut for advanced integrated circuit structure fabrication is described. For example, an integrated circuit structure includes a first fin segment having a fin end, and a second fin segment spaced apart from the first fin segment, the second fin segment having a fin end facing the fin end of the first fin segment. A first gate structure is over the first fin segment, the first gate structure substantially vertically aligned with the fin end of the first fin segment. A second gate structure is over the second fin segment, the second gate structure substantially vertically aligned with the fin end of the second fin segment. An isolation structure is laterally between the fin end of the first fin segment and the fin end of the second fin segment.

公开(公告)号：US20220390990A1

公开(公告)日：2022-12-08

申请号：US17339001

申请日：2021-06-04

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Mohammad HASAN ,  Charles H. WALLACE ,  Tahir GHANI ,  Robert JOACHIM ,  Shengsi LIU ,  Tsuan-Chung CHANG

IPC: G06F1/18 ,  H05K1/11 ,  G06F1/16

Abstract: Spacer self-aligned via structures for gate contact or trench contact are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. The integrated circuit structure also includes a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers between adjacent ones of the plurality of gate structures and the plurality of conductive trench contact structures, wherein the plurality of dielectric spacers protrudes above the plurality of gate structures and above the plurality of conductive trench contact structures. A conductive structure is in direct contact with one of the plurality of gate structures or with one of the plurality of conductive trench contact structures.

公开(公告)号：US20220093592A1

公开(公告)日：2022-03-24

申请号：US17030212

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Michael K. HARPER ,  William HSU ,  Biswajeet GUHA ,  Tahir GHANI ,  Niels ZUSSSBLATT ,  Jeffrey Miles TAN ,  Benjamin KRIEGEL ,  Mohit K. HARAN ,  Reken PATEL ,  Oleg GOLONZKA ,  Mohammad HASAN

IPC: H01L27/088 ,  H01L27/06 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  G11C5/06

Abstract: Gate-all-around integrated circuit structures having pre-spacer-deposition cut gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. The integrated circuit structure also includes a dielectric structure having a first portion forming a gate spacer along sidewalls of the first gate stack, a second portion forming a gate spacer along sidewalls of the second gate stack, and a third portion completely filling the gap, the third portion continuous with the first and second portions.