公开(公告)号：US20250062278A1

公开(公告)日：2025-02-20

申请号：US18452152

申请日：2023-08-18

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Debendra Mallik ,  Wilfred Gomes ,  Pushkar Sharad Ranade ,  Nitin A. Deshpande ,  Ravindranath Vithal Mahajan ,  Abhishek A. Sharma ,  Joshua Fryman ,  Stephen Morein ,  Matthew Adiletta ,  Michael Crocker ,  Aaron Gorius

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/522

Abstract: Embodiments of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including a conductive trace that is parallel to the first and second surfaces, and the conductive trace is exposed at the third surface; and a second IC die including a fourth surface, wherein the fourth surface of the second IC die is electrically coupled to the third surface of the first IC die by an interconnect including solder.

公开(公告)号：US12181710B2

公开(公告)日：2024-12-31

申请号：US17237375

申请日：2021-04-22

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Xiaoqian Li ,  Tarek A. Ibrahim ,  Ravindranath Vithal Mahajan ,  Nitin A. Deshpande

IPC: G02B6/122 ,  G02B6/12

Abstract: Photonic packages and device assemblies that include photonic integrated circuits (PICs) coupled to optical lenses on lateral sides of the PICs. An example photonic package comprises a package support, an integrated circuit (IC), an insulating material, a PIC having an active side and a lateral side substantially perpendicular to the active side. At least one optical structure is on the active side. A substantial portion of the active side is in contact with the insulating material, and the PIC is electrically coupled to the package support and to the IC. The photonic package further includes an optical lens coupled to the PIC on the lateral side. In some embodiments, the photonic package further includes an interposer between the PIC or the IC and the package support.

公开(公告)号：US12148742B2

公开(公告)日：2024-11-19

申请号：US16816669

申请日：2020-03-12

Applicant: Intel Corporation

Inventor： Thomas Liljeberg ,  Andrew C. Alduino ,  Ravindranath Vithal Mahajan ,  Ling Liao ,  Kenneth Brown ,  James Jaussi ,  Bharadwaj Parthasarathy ,  Nitin A Deshpande

IPC: G02B6/42 ,  H01L23/00 ,  H01L23/36 ,  H01L23/367 ,  H01L25/16 ,  H04B10/40

Abstract: Embodiments may relate to a microelectronic package that includes a package substrate with an active bridge positioned therein. An active die may be coupled with the package substrate, and communicatively coupled with the active bridge. A photonic integrated circuit (PIC) may also be coupled with the package substrate and communicatively coupled with the active bridge. Other embodiments may be described or claimed.

公开(公告)号：US20240222321A1

公开(公告)日：2024-07-04

申请号：US18148533

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Wilfred Gomes ,  Nisha Ananthakrishnan ,  Kemal Aygun ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Pushkar Sharad Ranade ,  Abhishek A. Sharma

IPC: H01L25/065

CPC classification number: H01L25/0652 ,  H01L2225/06548

Abstract: Embodiments of a microelectronic assembly include: a first integrated circuit (IC) die having a first memory circuit and a second memory circuit; a second IC die; a third IC die; and a package substrate. The second IC die is between the first IC die and the package substrate. The first IC die includes: a first portion comprising a first active region and a first backend region in contact with the first active region; and a second portion comprising a second active region and a second backend region in contact with the second active region. The first memory circuit is in the first portion, the second memory circuit is in the second portion, the first active region comprises transistors that are larger than transistors in the second active region, and the first backend region comprises conductive traces that have a larger pitch than conductive traces in the second backend region.

公开(公告)号：US20240178146A1

公开(公告)日：2024-05-30

申请号：US18060080

申请日：2022-11-30

Applicant: Intel Corporation

Inventor： Benjamin T. Duong ,  Whitney Bryks ,  Kristof Kuwawi Darmawikarta ,  Srinivas V. Pietambaram ,  Gang Duan ,  Ravindranath Vithal Mahajan

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/15 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/5384 ,  H01L23/15 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/13 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/13023 ,  H01L2924/15165 ,  H01L2924/15311

Abstract: Disclosed herein are microelectronic assemblies including strengthened glass cores, as well as related devices and methods. In some embodiments, a microelectronic assembly may include a glass core having a surface, a first region having a first concentration of ions extending from the surface of the core to a first depth; a second region having a second concentration of ions greater than the first concentration of ions, the second region between the first region and the surface of the core; a dielectric with a conductive pathway at the surface of the glass core; and a die electrically coupled to the conductive pathway in the dielectric at the surface of the core by an interconnect.

公开(公告)号：US20240006381A1

公开(公告)日：2024-01-04

申请号：US17854728

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Stephen Morein ,  Ravindranath Vithal Mahajan ,  Prashant Majhi

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2225/06548

Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a plurality of vertically stacked dies; a trench of dielectric material through the plurality of vertically stacked dies; and a plurality of conductive vias extending through the trench of dielectric material, wherein individual ones of the plurality of conductive vias are electrically coupled to individual ones of the plurality of vertically stacked dies.

公开(公告)号：US20240006366A1

公开(公告)日：2024-01-04

申请号：US17854613

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Stephen Morein ,  Ravindranath Vithal Mahajan ,  Prashant Majhi

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/24 ,  H01L2224/2405 ,  H01L24/20 ,  H01L2924/37001 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1443 ,  H01L2924/1431 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2924/15331 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/215 ,  H01L2224/24145 ,  H01L2224/24011 ,  H01L25/0652

Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a plurality of dies stacked vertically; a trench of dielectric material extending through the plurality of dies; a conductive via extending through the trench of dielectric material; and a plurality of conductive pathways between the plurality of dies and the conductive via, wherein individual ones of the conductive pathways are electrically coupled to the conductive via and to individual ones of the plurality of dies, and wherein the individual ones of the plurality of conductive pathways have a first portion including a first material and a second portion including a second material different from the first material.

公开(公告)号：US20230420436A1

公开(公告)日：2023-12-28

申请号：US17846109

申请日：2022-06-22

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Omkar G. Karhade ,  Wilfred Gomes ,  Pushkar Sharad Ranade ,  Abhishek A. Sharma ,  Tahir Ghani ,  Anand S. Murthy ,  Nitin A. Deshpande

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/522 ,  H01L23/48 ,  H01L25/00

CPC classification number: H01L25/18 ,  H01L24/08 ,  H01L23/5226 ,  H01L23/481 ,  H01L25/50 ,  H01L2224/08145

Abstract: Embodiments of an integrated circuit (IC) die comprise: a first region having a first surface; a second region attached to the first region along a first planar interface that is orthogonal to the first surface; and a third region attached to the second region along a second planar interface that is parallel to the first planar interface, the third region having a second surface, the second surface being coplanar with the first surface. The first region and the third region comprise a plurality of layers of conductive traces in a dielectric material, the conductive traces being orthogonal to the first and second surfaces; and bond-pads on the first and second surfaces, the bond-pads comprising portions of the respective conductive traces exposed on the first and second surfaces.