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公开(公告)号：US10269714B2
公开(公告)日：2019-04-23
申请号：US15257267
申请日：2016-09-06
发明人： John Bruley , Jack O. Chu , Kam-Leung Lee , Ahmet S. Ozcan , Paul M. Solomon , Jeng-bang Yau
IPC分类号： H01L23/535 , H01L23/532 , H01L29/78 , H01L21/768 , C22C30/00
摘要： A method of forming a contact to a semiconductor device is provided that forms an alloy composed of nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti) and a semiconductor material. The methods may include forming a nickel and platinum semiconductor alloy at a base of a via. A titanium layer having an angstrom scale thickness is deposited in the via in contact with the nickel platinum semiconductor alloy. An aluminum containing fill is deposited atop the titanium layer. A forming gas anneal including an oxygen containing atmosphere is applied to the structure to provide a contact alloy comprising nickel, platinum, aluminum, titanium and a semiconductor element from the contact surface of the semiconductor device.
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公开(公告)号：US20180175174A1
公开(公告)日：2018-06-21
申请号：US15383537
申请日：2016-12-19
IPC分类号： H01L29/66 , H01L21/265 , H01L29/10 , H01L29/207
CPC分类号： H01L29/66803 , H01L21/26546 , H01L21/26586 , H01L29/1041 , H01L29/207
摘要： Embodiments are directed to a method of forming a semiconductor device and resulting structures having a shallow, abrupt and highly activated tin (Sn) extension implant junction. The method includes forming a semiconductor fin on a substrate. A gate is formed over a channel region of the semiconductor fin. A Sn extension implant junction is formed on a surface of the semiconductor fin in the channel region.
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23.发明申请公开(公告)号：US20170309723A1
公开(公告)日：2017-10-26
申请号：US15474482
申请日：2017-03-30
发明人： Takashi Ando , John Bruley , Eduard A. Cartier , Martin M. Frank , Vijay Narayanan , John Rozen
IPC分类号： H01L29/51 , H01L29/66 , H01L29/78 , H01L29/417
CPC分类号： H01L21/28255 , H01L21/28229 , H01L21/28264 , H01L29/401 , H01L29/41725 , H01L29/517 , H01L29/66522 , H01L29/66545 , H01L29/66795 , H01L29/78 , H01L29/785
摘要： A method of forming a semiconductor device that includes forming a metal oxide material on a III-V semiconductor channel region or a germanium containing channel region; and treating the metal oxide material with an oxidation process. The method may further include depositing of a hafnium containing oxide on the metal oxide material after the oxidation process, and forming a gate conductor atop the hafnium containing oxide. The source and drain regions are on present on opposing sides of the gate structure including the metal oxide material, the hafnium containing oxide and the gate conductor.
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公开(公告)号：US09324843B2
公开(公告)日：2016-04-26
申请号：US14479252
申请日：2014-09-05
发明人： Karthik Balakrishnan , John Bruley , Pouya Hashemi , Ali Khakifirooz , John A. Ott , Alexander Reznicek
IPC分类号： H01L21/8238 , H01L29/66 , H01L29/78 , H01L29/161 , H01L21/306 , H01L21/311 , H01L21/324 , H01L29/06
CPC分类号： H01L29/161 , H01L21/18 , H01L21/30604 , H01L21/31144 , H01L21/324 , H01L27/0886 , H01L29/0649 , H01L29/0657 , H01L29/1054 , H01L29/66818 , H01L29/785
摘要： Thermal condensation is employed to obtain a finned structure including strained silicon germanium fins having vertical side walls and a germanium content that may be high relative to silicon. A hard mask is used directly on a low-germanium content silicon germanium layer. The hard mask is patterned and fins are formed beneath the hard mask from the silicon germanium layer. Thermal condensation in an oxidizing ambient causes the formation of regions beneath the hard mask that have a high germanium content. The hard mask is trimmed to a target critical dimension. The regions beneath the hard mask and adjoining oxide material are subjected to reactive ion etch, resulting in the formation of high-germanium content fins with planar, vertically extending sidewalls.
摘要翻译： 使用热凝结来获得包括具有垂直侧壁的应变硅锗翅片和相对于硅可能高的锗含量的翅片结构。 硬掩模直接用于低锗含量的硅锗层上。 硬掩模被图案化，并且翅片从硬质掩模形成在硅锗层的下方。 在氧化环境中的热凝结导致形成具有高锗含量的硬掩模下面的区域。 硬面罩被修剪到目标临界尺寸。 硬掩模和毗邻的氧化物材料之下的区域经受反应离子蚀刻，导致形成具有平面的垂直延伸的侧壁的高锗含量的翅片。
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公开(公告)号：US12062614B2
公开(公告)日：2024-08-13
申请号：US17374327
申请日：2021-07-13
发明人： John Bruley , Jack O. Chu , Kam-Leung Lee , Ahmet S. Ozcan , Paul M. Solomon , Jeng-Bang Yau
IPC分类号： H01L23/535 , C22C30/00 , H01L21/285 , H01L21/768 , H01L23/485 , H01L23/532 , H01L29/78
CPC分类号： H01L23/535 , C22C30/00 , H01L21/28518 , H01L21/2855 , H01L21/76805 , H01L21/76843 , H01L21/76846 , H01L21/76858 , H01L21/76864 , H01L21/76895 , H01L23/485 , H01L23/53223 , H01L23/53266 , H01L29/7851 , H01L23/53209 , H01L23/53238 , H01L23/53252
摘要： A method of forming a contact to a semiconductor device is provided that forms an alloy composed of nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti) and a semiconductor material. The methods may include forming a nickel and platinum semiconductor alloy at a base of a via. A titanium layer having an angstrom scale thickness is deposited in the via in contact with the nickel platinum semiconductor alloy. An aluminum containing fill is deposited atop the titanium layer. A forming gas anneal including an oxygen containing atmosphere is applied to the structure to provide a contact alloy comprising nickel, platinum, aluminum, titanium and a semiconductor element from the contact surface of the semiconductor device.
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公开(公告)号：US20240244982A1
公开(公告)日：2024-07-18
申请号：US18097194
申请日：2023-01-13
摘要： Magnetic tunnel junction pillars including ordered alloy, bottom free layers are formed using simplified seed structures including textured magnesium oxide. The seed structures can have relatively small thicknesses, thereby reducing roughness of layers formed above the seed structures and facilitating magnetic tunnel junction pillar formation from multi-layer films including such seed structures.
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公开(公告)号：US11862567B2
公开(公告)日：2024-01-02
申请号：US17196267
申请日：2021-03-09
发明人： John Bruley , Jack O. Chu , Kam-Leung Lee , Ahmet S. Ozcan , Paul M. Solomon , Jeng-bang Yau
IPC分类号： H01L23/535 , H01L23/532 , H01L29/78 , H01L21/768 , C22C30/00 , H01L23/485 , H01L21/285
CPC分类号： H01L23/535 , C22C30/00 , H01L21/2855 , H01L21/28518 , H01L21/76805 , H01L21/76843 , H01L21/76846 , H01L21/76858 , H01L21/76864 , H01L21/76895 , H01L23/485 , H01L23/53223 , H01L23/53266 , H01L29/7851 , H01L23/53209 , H01L23/53238 , H01L23/53252
摘要： A method of forming a contact to a semiconductor device is provided that forms an alloy composed of nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti) and a semiconductor material. The methods may include forming a nickel and platinum semiconductor alloy at a base of a via. A titanium layer having an angstrom scale thickness is deposited in the via in contact with the nickel platinum semiconductor alloy. An aluminum containing fill is deposited atop the titanium layer. A forming gas anneal including an oxygen containing atmosphere is applied to the structure to provide a contact alloy comprising nickel, platinum, aluminum, titanium and a semiconductor element from the contact surface of the semiconductor device.
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公开(公告)号：US11765985B2
公开(公告)日：2023-09-19
申请号：US16908120
申请日：2020-06-22
发明人： Vivekananda P. Adiga , Martin O. Sandberg , Jeng-Bang Yau , Keith Fogel , John Bruley , Markus Brink , Benjamin Wymore
CPC分类号： H10N60/0912 , H10N60/12 , H10N60/805
摘要： Systems and techniques that facilitate spurious junction prevention via in-situ ion milling are provided. In various embodiments, a method can comprise forming a tunnel barrier of a Josephson junction on a substrate during a shadow evaporation process. In various instances, the method can further comprise etching an exposed portion of the tunnel barrier during the shadow evaporation process. In various embodiments, the shadow evaporation process can comprise patterning a resist stack onto the substrate. In various instances, the etching the exposed portion of the tunnel barrier can leave a protected portion of the tunnel barrier within a shadow of the resist stack. In various instances, the shadow of the resist stack can be based on a direction of the etching the exposed portion of the tunnel barrier. In various embodiments, the shadow evaporation process can further comprise depositing a first superconducting material on the substrate after the patterning the resist stack, oxidizing a surface of the first superconducting material to form the tunnel barrier, and depositing a second superconducting material over the protected portion of the tunnel barrier to form a Josephson junction. In various instances, the etching the exposed portion of the tunnel barrier can occur after the oxidizing the surface of the first superconducting material and before the depositing the second superconducting material.
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公开(公告)号：US20220123195A1
公开(公告)日：2022-04-21
申请号：US17071528
申请日：2020-10-15
发明人： Vivekananda P. Adiga , Martin S. Sandberg , Jeng-Bang Yau , David L. Rath , John Bruley , Cihan Kurter , Kenneth P. Rodbell , Hongwen Yan
摘要： Devices, systems, methods, and/or computer-implemented methods that can facilitate protection of a substrate in a qubit device using sacrificial material are provided. According to an embodiment, a device can comprise a superconducting lead provided on a pillar of a sacrificial material provided on a substrate. The device can further comprise a collapsed superconducting junction provided on the substrate and coupled to the superconducting lead.
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公开(公告)号：US10985105B2
公开(公告)日：2021-04-20
申请号：US16168092
申请日：2018-10-23
发明人： John Bruley , Jack O. Chu , Kam-Leung Lee , Ahmet S. Ozcan , Paul M. Solomon , Jeng-bang Yau
IPC分类号： H01L23/535 , H01L23/532 , H01L29/78 , H01L21/768 , C22C30/00 , H01L23/485 , H01L21/285
摘要： A method of forming a contact to a semiconductor device is provided that forms an alloy composed of nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti) and a semiconductor material. The methods may include forming a nickel and platinum semiconductor alloy at a base of a via. A titanium layer having an angstrom scale thickness is deposited in the via in contact with the nickel platinum semiconductor alloy. An aluminum containing fill is deposited atop the titanium layer. A forming gas anneal including an oxygen containing atmosphere is applied to the structure to provide a contact alloy comprising nickel, platinum, aluminum, titanium and a semiconductor element from the contact surface of the semiconductor device.
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