公开(公告)号：US08963291B2

公开(公告)日：2015-02-24

申请号：US13112738

申请日：2011-05-20

申请人： Takeshi Furusawa ,  Noriko Miura ,  Kinya Goto ,  Masazumi Matsuura

发明人： Takeshi Furusawa ,  Noriko Miura ,  Kinya Goto ,  Masazumi Matsuura

IPC分类号： H01L21/56

CPC分类号： H01L23/585 ,  H01L23/3192 ,  H01L23/53295 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device including a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls forming a closed loop in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.

摘要翻译： 包括相对介电常数小于3.5的低介电常数膜的半导体器件设置有一个或多个密封环，该密封环是在平面图中形成闭环的防潮壁，并且其中至少一个密封件 环在芯片角附近包括向内突出形式的密封环突出部。

公开(公告)号：US08018030B2

公开(公告)日：2011-09-13

申请号：US12410170

申请日：2009-03-24

申请人： Takeshi Furusawa ,  Noriko Miura ,  Kinya Goto ,  Masazumi Matsuura

发明人： Takeshi Furusawa ,  Noriko Miura ,  Kinya Goto ,  Masazumi Matsuura

IPC分类号： H01L21/56

CPC分类号： H01L23/585 ,  H01L23/3192 ,  H01L23/53295 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device according to the invention is a semiconductor device which includes a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls in closed loop form in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.

摘要翻译： 根据本发明的半导体器件是一种半导体器件，其包括相对介电常数小于3.5的低介电常数膜，在平面图中设置有一个或多个密闭环，其为闭环形式的防潮壁 并且其中至少一个所述密封环包括在芯片角附近以向内突出形式的密封环突出部分。

公开(公告)号：US07960279B2

公开(公告)日：2011-06-14

申请号：US12493347

申请日：2009-06-29

申请人： Takeshi Furusawa ,  Noriko Miura ,  Kinya Goto ,  Masazumi Matsuura

发明人： Takeshi Furusawa ,  Noriko Miura ,  Kinya Goto ,  Masazumi Matsuura

IPC分类号： H01L21/44

CPC分类号： H01L21/76802 ,  H01L21/02074 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/3105 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76835 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： In a semiconductor having a multilayer wiring structure device on a semiconductor substrate, the multilayer wiring structure includes an interlayer insulating film having at least an organic siloxane insulating film. The organic siloxane insulating film has a relative dielectric constant of 3.1 or less, a hardness of 2.7 GPa or more, and a ratio of carbon atoms to silicon atoms between 0.5 and 1.0, inclusive. Further, the multilayer wiring structure may include an insulating layer having a ratio of carbon atoms to silicon atoms not greater than 0.1, the insulating layer being formed on the top surface of the organic siloxane insulating film as a result of carbon leaving the organic siloxane insulating film.

摘要翻译： 在半导体衬底上具有多层布线结构器件的半导体中，多层布线结构包括至少具有有机硅氧烷绝缘膜的层间绝缘膜。 有机硅氧烷绝缘膜的相对介电常数为3.1以下，硬度为2.7GPa以上，碳原子与硅原子的比例在0.5以上且1.0以下。 此外，多层布线结构可以包括碳原子与硅原子之比不大于0.1的绝缘层，绝缘层由有机硅氧烷绝缘膜的碳离子形成在有机硅氧烷绝缘膜的顶表面上 电影。

公开(公告)号：US20070114668A1

公开(公告)日：2007-05-24

申请号：US11561629

申请日：2006-11-20

申请人： Kinya Goto ,  Takeshi Furusawa ,  Masazumi Matsuura ,  Noriko Miura

发明人： Kinya Goto ,  Takeshi Furusawa ,  Masazumi Matsuura ,  Noriko Miura

IPC分类号： H01L23/52

CPC分类号： H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05147 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2224/48799 ,  H01L2224/49175 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/00 ,  H01L2224/48824 ,  H01L2924/00015

摘要： A semiconductor device is equipped with a semiconductor chip which has at least one layer of first insulating film formed on a substrate, and a plurality of pads arranged on a layer higher than the first insulating film. The plurality of pads on the semiconductor chip are arranged parallel to a predetermined chip edge of the semiconductor chip. The first insulating film has a reinforcement pattern in a region underneath each of the plurality of pads. In the region underneath each pad, occupancy of the reinforcement pattern in the first insulating film is within a predetermined range permitted for the region underneath each pad and occupancy of the reinforcement pattern in a whole area of a row where the reinforcement pattern is arranged in a line in a direction perpendicular to the predetermined chip edge is higher than occupancy of the reinforcement pattern in a whole area of a row where the reinforcement pattern is arranged in a line in a direction parallel to the chip edge.

摘要翻译： 半导体器件配备有半导体芯片，该半导体芯片具有形成在基板上的至少一层第一绝缘膜，以及布置在高于第一绝缘膜的层上的多个焊盘。 半导体芯片上的多个焊盘平行于半导体芯片的预定的芯片边缘布置。 第一绝缘膜在多个焊盘中的每一个下方的区域中具有加强图案。 在每个垫下面的区域中，第一绝缘膜中的加强图案的占用在每个垫下面的区域允许的预定范围内，并且在加强图案布置在一排中的整个区域中的加强图案的占用 在垂直于预定芯片边缘的方向上的线在高于在与芯片边缘平行的方向上排列成一列的行的整个区域中的加强图案的占有率高。