公开(公告)号：US20100109046A1

公开(公告)日：2010-05-06

申请号：US12290809

申请日：2008-11-03

申请人： Rishabh Mehandru ,  Bernhard Sell ,  Anand Murthy ,  Lucian Shifren

发明人： Rishabh Mehandru ,  Bernhard Sell ,  Anand Murthy ,  Lucian Shifren

IPC分类号： H01L29/778 ,  H01L21/336

CPC分类号： H01L21/26513 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/76804 ,  H01L21/76814 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7834

摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a tapered contact opening in an ILD disposed on a substrate, wherein a source/drain contact area is exposed, preamorphizing a portion of a source drain region of the substrate, implanting boron into the source/drain region through the tapered contact opening, forming a metal layer on the source/drain contact area, and then annealing the metal layer to form a metal silicide.

摘要翻译： 描述形成微电子器件的方法和相关结构。 这些方法可以包括在设置在衬底上的ILD中形成锥形接触开口，其中暴露源极/漏极接触区域，对基底的源极漏极区域的一部分进行预变质，通过锥形 接触开口，在源极/漏极接触区域上形成金属层，然后退火金属层以形成金属硅化物。

公开(公告)号：US20090085097A1

公开(公告)日：2009-04-02

申请号：US11863116

申请日：2007-09-27

申请人： Lucian Shifren ,  Keith E. Zawadzki

发明人： Lucian Shifren ,  Keith E. Zawadzki

IPC分类号： H01L29/94 ,  H01L21/311

CPC分类号： H01L21/823807 ,  H01L21/28079 ,  H01L21/3185 ,  H01L29/495 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7843

摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may include removing residual dielectric material from a metal gate structure, and then forming a stress relief layer on a top surface and on a sidewall region of the metal gate structure. A stress is introduced into a channel region disposed beneath the metal gate structure.

摘要翻译： 描述形成微电子器件的方法和相关结构。 这些方法可以包括从金属栅极结构去除残余介电材料，然后在金属栅极结构的顶表面和侧壁区上形成应力消除层。 将应力引入设置在金属栅极结构下方的沟道区域中。

公开(公告)号：US08748270B1

公开(公告)日：2014-06-10

申请号：US13553902

申请日：2012-07-20

申请人： Lucian Shifren ,  Scott E. Thompson ,  Paul E. Gregory

发明人： Lucian Shifren ,  Scott E. Thompson ,  Paul E. Gregory

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/66659 ,  H01L21/823412 ,  H01L21/823456 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/7835 ,  H01L29/7836

摘要： An analog transistor useful for low noise applications or for electrical circuits benefiting from tight control of threshold voltages and electrical characteristics is described. The analog transistor includes a substantially undoped channel positioned under a gate dielectric between a source and a drain with the undoped channel not being subjected to contaminating threshold voltage implants or halo implants. The channel is supported on a screen layer doped to have an average dopant density at least five times as great as the average dopant density of the substantially undoped channel which, in turn, is supported by a doped well having an average dopant density at least twice the average dopant density of the substantially undoped channel.

摘要翻译： 描述了一种用于低噪声应用的模拟晶体管或有益于阈值电压和电特性的严格控制的电路。 模拟晶体管包括位于源极和漏极之间的栅极电介质下方的基本上未掺杂的沟道，未掺杂沟道不经受污染阈值电压注入或晕轮植入。 该通道被支撑在被掺杂以使平均掺杂剂密度为基本上未掺杂的沟道的平均掺杂剂密度的至少五倍的屏蔽层上，该掺杂剂密度又由具有至少两倍的平均掺杂剂密度的掺杂阱支持 基本上未掺杂的通道的平均掺杂剂密度。

公开(公告)号：US20140103406A1

公开(公告)日：2014-04-17

申请号：US14133743

申请日：2013-12-19

申请人： Lingquan Wang ,  Teymur Bakhishev ,  Dalong Zhao ,  Pushkar Ranade ,  Sameer Pradhan ,  Thomas Hoffmann ,  Lucian Shifren ,  Lance Scudder

发明人： Lingquan Wang ,  Teymur Bakhishev ,  Dalong Zhao ,  Pushkar Ranade ,  Sameer Pradhan ,  Thomas Hoffmann ,  Lucian Shifren ,  Lance Scudder

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/78 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823481 ,  H01L27/092 ,  H01L29/105 ,  H01L29/66477 ,  H01L29/6659

摘要： A semiconductor structure is formed with a NFET device and a PFET device. The NFET device is formed by masking the PFET device regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. The PFET device is similarly formed by masking the NFET regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. An isolation region is formed between the NFET and the PFET device areas to remove any facets occurring during the separate epitaxial growth phases. By forming the screen layer through in-situ doped epitaxial growth, a reduction in junction leakage is achieved versus forming the screen layer using ion implantation.

摘要翻译： 半导体结构由NFET器件和PFET器件形成。 通过掩蔽衬底的PFET器件区域，通过外延生长和原位掺杂形成屏蔽层，并通过外延生长在屏蔽层上形成未掺杂沟道层，形成NFET器件。 PFET器件类似地通过掩蔽衬底的NFET区域，通过外延生长和原位掺杂形成屏蔽层，并通过外延生长在屏幕层上形成未掺杂沟道层。 在NFET和PFET器件区域之间形成隔离区以去除在单独外延生长阶段期间发生的任何刻面。 通过原位掺杂外延生长形成屏蔽层，相对于使用离子注入形成屏幕层，实现了结漏电减少。

公开(公告)号：US08637955B1

公开(公告)日：2014-01-28

申请号：US13600647

申请日：2012-08-31

申请人： Lingquan Wang ,  Teymur Bakhishev ,  Dalong Zhao ,  Pushkar Ranade ,  Sameer Pradhan ,  Thomas Hoffmann ,  Lucian Shifren ,  Lance Scudder

发明人： Lingquan Wang ,  Teymur Bakhishev ,  Dalong Zhao ,  Pushkar Ranade ,  Sameer Pradhan ,  Thomas Hoffmann ,  Lucian Shifren ,  Lance Scudder

IPC分类号： H01L29/15 ,  H01L29/167 ,  H01L29/36

CPC分类号： H01L29/78 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823481 ,  H01L27/092 ,  H01L29/105 ,  H01L29/66477 ,  H01L29/6659

摘要： A semiconductor structure is formed with a NFET device and a PFET device. The NFET device is formed by masking the PFET device regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. The PFET device is similarly formed by masking the NFET regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. An isolation region is formed between the NFET and the PFET device areas to remove any facets occurring during the separate epitaxial growth phases. By forming the screen layer through in-situ doped epitaxial growth, a reduction in junction leakage is achieved versus forming the screen layer using ion, implantation.

摘要翻译： 半导体结构由NFET器件和PFET器件形成。 通过掩蔽衬底的PFET器件区域，通过外延生长和原位掺杂形成屏蔽层，并通过外延生长在屏蔽层上形成未掺杂沟道层，形成NFET器件。 PFET器件类似地通过掩蔽衬底的NFET区域，通过外延生长和原位掺杂形成屏蔽层，并通过外延生长在屏幕层上形成未掺杂沟道层。 在NFET和PFET器件区域之间形成隔离区以去除在单独外延生长阶段期间发生的任何刻面。 通过通过原位掺杂的外延生长形成屏蔽层，相对于使用离子注入形成屏幕层，实现了结漏电减少。

公开(公告)号：US08629016B1

公开(公告)日：2014-01-14

申请号：US13459971

申请日：2012-04-30

申请人： Thomas Hoffmann ,  Pushkar Ranade ,  Lucian Shifren ,  Scott E. Thompson

发明人： Thomas Hoffmann ,  Pushkar Ranade ,  Lucian Shifren ,  Scott E. Thompson

IPC分类号： H01L21/8238

CPC分类号： H01L21/22 ,  H01L21/28255 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/66477 ,  H01L29/78

摘要： Multiple transistor types are formed in a common epitaxial layer by differential out-diffusion from a doped underlayer. Differential out-diffusion affects the thickness of a FET channel, the doping concentration in the FET channel, and distance between the gate dielectric layer and the doped underlayer. Differential out-diffusion may be achieved by differentially applying a dopant migration suppressor such as carbon; differentially doping the underlayer with two or more dopants having the same conductivity type but different diffusivities; and/or differentially applying thermal energy.

摘要翻译： 通过从掺杂底层的差分向外扩散，在公共外延层中形成多晶体管类型。 差分外扩散影响FET沟道的厚度，FET沟道中的掺杂浓度以及栅介质层与掺杂底层之间的距离。 差分外扩散可以通过差分施加掺杂剂迁移抑制剂如碳来实现; 用具有相同导电类型但不同扩散性的两种或更多种掺杂剂差异掺杂底层; 和/或差异地施加热能。

公开(公告)号：US08377783B2

公开(公告)日：2013-02-19

申请号：US12895695

申请日：2010-09-30

申请人： Lucian Shifren ,  Taiji Ema

发明人： Lucian Shifren ,  Taiji Ema

IPC分类号： H01L21/336

CPC分类号： H01L29/1083 ,  H01L27/0921

摘要： Punch-through in a transistor device is reduced by forming a well layer in an implant region, forming a stop layer in the well layer of lesser depth than the well layer, and forming a doped layer in the stop layer of lesser depth than the stop layer. The stop layer has a lower concentration of impurities than the doped layer in order to prevent punch-through without increasing junction leakage.

摘要翻译： 在晶体管器件中的穿通通过在注入区域中形成阱层而减少，在阱层中形成比阱层更深的阱层中的阻挡层，以及在比止蚀层更深的深度的阻挡层中形成掺杂层 层。 阻止层的杂质浓度比掺杂层低，以防止穿通而不增加结漏电。

公开(公告)号：US20120223389A1

公开(公告)日：2012-09-06

申请号：US13039986

申请日：2011-03-03

申请人： Paul E. Gregory ,  Lucian Shifren ,  Pushkar Ranade

发明人： Paul E. Gregory ,  Lucian Shifren ,  Pushkar Ranade

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L27/0928 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/665 ,  H01L29/66651 ,  H01L29/7833

摘要： A method for fabricating a semiconductor structure with a channel stack includes forming a screening layer under a gate of a PMOS transistor element and a NMOS transistor element, forming a threshold voltage control layer on the screening layer, and forming an epitaxial channel layer on the threshold control layer. At least a portion of the epitaxial channel layers for the PMOS transistor element and the NMOS transistor element are formed as a common blanket layer. The screening layer for the PMOS transistor element may include antimony as a dopant material that may be inserted into the structure prior to or after formation of the epitaxial channel layer.

摘要翻译： 一种用于制造具有沟道堆叠的半导体结构的方法，包括在PMOS晶体管元件和NMOS晶体管元件的栅极下形成屏蔽层，在屏蔽层上形成阈值电压控制层，并在阈值上形成外延沟道层 控制层。 用于PMOS晶体管元件和NMOS晶体管元件的至少一部分外延沟道层形成为公共覆盖层。 用于PMOS晶体管元件的屏蔽层可以包括锑作为可以在形成外延沟道层之前或之后插入结构中的掺杂材料。

公开(公告)号：US20110309447A1

公开(公告)日：2011-12-22

申请号：US12971955

申请日：2010-12-17

申请人： Reza Arghavani ,  Pushkar Ranade ,  Lucian Shifren ,  Scott E. Thompson ,  Catherine de Villeneuve

发明人： Reza Arghavani ,  Pushkar Ranade ,  Lucian Shifren ,  Scott E. Thompson ,  Catherine de Villeneuve

IPC分类号： H01L27/088 ,  H01L21/76

CPC分类号： H01L27/0921 ,  H01L21/823412 ,  H01L21/82345 ,  H01L21/823493 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/36 ,  H01L29/365 ,  H01L29/4966 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7836

摘要： A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. A novel dopant profile indicative of a distinctive notch enables tuning of the VT setting within a precise range. This VT set range may be extended by appropriate selection of metals so that a very wide range of VT settings is accommodated on the die. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The result is the ability to independently control VT (with a low σVT) and VDD, so that the body bias can be tuned separately from VT for a given device.

摘要翻译： 其制造的结构和方法涉及深度消耗通道（DDC）设计，允许基于CMOS的器件与常规体CMOS相比具有减小的VT，并且可以允许在沟道区中具有掺杂剂的FET的阈值电压VT 更精确地设置。 指示特征性缺口的新型掺杂物分布使得能够在精确范围内调整VT设置。 可以通过适当选择金属来扩展该VT设定范围，使得在管芯上容纳非常宽范围的VT设置。 与传统的体积CMOS晶体管相比，DDC设计也可以具有强大的机身效应，可以显着地动态控制DDC晶体管的功耗。 结果是能够独立地控制VT（具有低电平（VT））和VDD（VDD），从而使给定器件的体偏压可以与VT分开调谐。

公开(公告)号：US20090315120A1

公开(公告)日：2009-12-24

申请号：US12145296

申请日：2008-06-24

申请人： Lucian Shifren ,  Keith Zawadzki ,  Martin Giles ,  Cory Weber

发明人： Lucian Shifren ,  Keith Zawadzki ,  Martin Giles ,  Cory Weber

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7834 ,  H01L29/66628

摘要： An apparatus comprising a semiconductor substrate; a conductively doped source or drain (source/drain) region at the surface of the substrate; a raised semiconductor layer deposited over the source/drain region to form a raised source/drain region; a via formed in the raised source/drain region having substantially vertical sidewalls reaching partly or substantially to the source/drain region; and a metal contact filling the via.

摘要翻译： 一种包括半导体衬底的装置; 在衬底的表面处的导电掺杂源极或漏极（源极/漏极）区域; 沉积在源极/漏极区域上以形成升高的源极/漏极区域的凸起的半导体层; 在凸起的源极/漏极区域中形成的通孔具有基本上垂直的侧壁，部分地或基本上相对于源极/漏极区域; 以及填充通孔的金属接触件。