公开(公告)号：US20100109046A1

公开(公告)日：2010-05-06

申请号：US12290809

申请日：2008-11-03

申请人： Rishabh Mehandru ,  Bernhard Sell ,  Anand Murthy ,  Lucian Shifren

发明人： Rishabh Mehandru ,  Bernhard Sell ,  Anand Murthy ,  Lucian Shifren

IPC分类号： H01L29/778 ,  H01L21/336

CPC分类号： H01L21/26513 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/76804 ,  H01L21/76814 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7834

摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a tapered contact opening in an ILD disposed on a substrate, wherein a source/drain contact area is exposed, preamorphizing a portion of a source drain region of the substrate, implanting boron into the source/drain region through the tapered contact opening, forming a metal layer on the source/drain contact area, and then annealing the metal layer to form a metal silicide.

摘要翻译： 描述形成微电子器件的方法和相关结构。 这些方法可以包括在设置在衬底上的ILD中形成锥形接触开口，其中暴露源极/漏极接触区域，对基底的源极漏极区域的一部分进行预变质，通过锥形 接触开口，在源极/漏极接触区域上形成金属层，然后退火金属层以形成金属硅化物。

公开(公告)号：US20120068180A1

公开(公告)日：2012-03-22

申请号：US13292865

申请日：2011-11-09

申请人： Rishabh Mehandru ,  Bernhard Sell ,  Anand Murthy ,  Lucian Shifren

发明人： Rishabh Mehandru ,  Bernhard Sell ,  Anand Murthy ,  Lucian Shifren

IPC分类号： H01L29/78

CPC分类号： H01L21/26513 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/76804 ,  H01L21/76814 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7834

摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a tapered contact opening in an ILD disposed on a substrate, wherein a source/drain contact area is exposed, preamorphizing a portion of a source drain region of the substrate, implanting boron into the source/drain region through the tapered contact opening, forming a metal layer on the source/drain contact area, and then annealing the metal layer to form a metal silicide.

摘要翻译： 描述形成微电子器件的方法和相关结构。 这些方法可以包括在设置在衬底上的ILD中形成锥形接触开口，其中暴露源极/漏极接触区域，对基底的源极漏极区域的一部分进行预变质，通过锥形 接触开口，在源极/漏极接触区域上形成金属层，然后退火金属层以形成金属硅化物。

公开(公告)号：US20110147840A1

公开(公告)日：2011-06-23

申请号：US12646651

申请日：2009-12-23

申请人： Stephen M. Cea ,  Rishabh Mehandru ,  Lucian Shifren ,  Kelin Kuhn

发明人： Stephen M. Cea ,  Rishabh Mehandru ,  Lucian Shifren ,  Kelin Kuhn

IPC分类号： H01L27/12 ,  H01L21/86

CPC分类号： H01L29/785 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7848 ,  H01L2029/7858

摘要： A semiconductor device comprises a substrate and a semiconductor body formed on the substrate. The semiconductor body comprises a source region; and a drain region. The source region or the drain region, or combinations thereof, comprises a first side surface, a second side surface, and a top surface. The first side surface is opposite the second side surface, the top surface is opposite the bottom surface. The source region or the drain region, or combinations thereof, comprise a metal layer formed on the substantially all of the first side surface, substantially all of the second side surface, and the top surface.

摘要翻译： 半导体器件包括形成在衬底上的衬底和半导体本体。 半导体主体包括源极区域; 和漏区。 源区或漏区，或其组合包括第一侧表面，第二侧表面和顶表面。 第一侧表面与第二侧表面相对，顶表面与底表面相对。 源极区域或漏极区域或其组合包括形成在基本上所有第一侧表面上的基本上所有的第二侧表面和顶表面上的金属层。

公开(公告)号：US08883600B1

公开(公告)日：2014-11-11

申请号：US13725152

申请日：2012-12-21

申请人： Scott E. Thompson ,  Lucian Shifren ,  Pushkar Ranade ,  Yujie Liu ,  Sung Hwan Kim ,  Lingquan Wang ,  Dalong Zhao ,  Teymur Bakhishev ,  Thomas Hoffmann ,  Sameer Pradhan ,  Michael Duane

发明人： Scott E. Thompson ,  Lucian Shifren ,  Pushkar Ranade ,  Yujie Liu ,  Sung Hwan Kim ,  Lingquan Wang ,  Dalong Zhao ,  Teymur Bakhishev ,  Thomas Hoffmann ,  Sameer Pradhan ,  Michael Duane

IPC分类号： H01L21/331 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/7833 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/0847 ,  H01L29/1041 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7836

摘要： A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control.

摘要翻译： 晶体管及其制造方法包括至少部分地形成在沟道层和栅极堆叠下方的半导体衬底中的屏蔽层，栅极堆叠包括在栅极叠层的任一侧上的间隔结构。 晶体管包括沟道层中的浅掺杂稀土漏极区和相对于屏蔽层底部的深度处的深掺杂漏极区，用于减少结漏电流。 还可以包括补偿层以防止背栅控制的损失。

公开(公告)号：US08748986B1

公开(公告)日：2014-06-10

申请号：US13559554

申请日：2012-07-26

申请人： Lucian Shifren ,  Pushkar Ranade

发明人： Lucian Shifren ,  Pushkar Ranade

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/786 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78696

摘要： Structures and methods of fabrication thereof related to an improved semiconductor on insulator (SOI) transistor formed on an SOI substrate. The improved SOI transistor includes a substantially undoped channel extending between the source and the drain, an optional threshold voltage set region positioned below the substantially undoped channel, and a screening region positioned below the threshold voltage set region. The threshold voltage of the improved SOI transistor can be adjusted without halo implants or threshold voltage implants into the channel, using the position and/or dopant concentration of the screening region and/or the threshold voltage set region.

摘要翻译： 其结构及其制造方法涉及形成在SOI衬底上的改进的绝缘体上半导体（SOI）晶体管。 改进的SOI晶体管包括在源极和漏极之间延伸的基本上未掺杂的沟道，位于基本上未掺杂沟道下方的可选阈值电压设置区域和位于阈值电压设置区域下方的屏蔽区域。 可以使用屏蔽区域和/或阈值电压设置区域的位置和/或掺杂剂浓度来调整改进的SOI晶体管的阈值电压而无需光晕注入或阈值电压注入到沟道中。

公开(公告)号：US20130161743A1

公开(公告)日：2013-06-27

申请号：US13770313

申请日：2013-02-19

申请人： Pushkar Ranade ,  Lucian Shifren ,  Sachin R. Sonkusale

发明人： Pushkar Ranade ,  Lucian Shifren ,  Sachin R. Sonkusale

IPC分类号： H01L29/78 ,  H01L27/085

CPC分类号： H01L29/7816 ,  H01L27/085 ,  H01L27/088 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7848

摘要： A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×1019 atoms/cm3′, or alternatively, less than one-quarter the dopant concentration of the source and the drain.

摘要翻译： 具有改进性能的平面晶体管在半导体衬底上具有源极和漏极，其包括在源极和漏极之间延伸的基本上未掺杂的沟道。 栅极位于衬底上的基本上未掺杂的沟道上。 注入源极/漏极延伸部接触源极和漏极，注入源极/漏极延伸部的掺杂剂浓度小于约1×1019原子/ cm3'，或者可选地，小于源极的掺杂剂浓度的四分之一，以及 排水。

公开(公告)号：US20120083103A1

公开(公告)日：2012-04-05

申请号：US12895657

申请日：2010-09-30

申请人： Lucian Shifren ,  Taiji Ema

发明人： Lucian Shifren ,  Taiji Ema

IPC分类号： H01L21/26

CPC分类号： H01L21/26513 ,  H01L21/26506 ,  H01L21/324

摘要： Defects in a semiconductor substrate due to ion implantation are minimized by forming an implant region in the semiconductor substrate and subjecting the semiconductor substrate to a first anneal to recrystallize the semiconductor substrate. The semiconductor substrate is subjected to a second anneal to suppress diffusion of implanted ions in the semiconductor substrate. The first anneal being at a lower temperature and longer duration than the second anneal.

摘要翻译： 通过在半导体衬底中形成注入区域并对半导体衬底进行第一次退火以使半导体衬底再结晶，使离子注入在半导体衬底中的缺陷最小化。 对半导体衬底进行第二退火以抑制注入离子在半导体衬底中的扩散。 第一退火处于比第二退火更低的温度和更长的持续时间。

公开(公告)号：US20110121404A1

公开(公告)日：2011-05-26

申请号：US12895813

申请日：2010-09-30

申请人： Lucian Shifren ,  Pushkar Ranade ,  Paul E. Gregory ,  Sachin R. Sonkusale ,  Weimin Zhang

发明人： Lucian Shifren ,  Pushkar Ranade ,  Paul E. Gregory ,  Sachin R. Sonkusale ,  Weimin Zhang

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/1083 ,  H01L21/823412 ,  H01L21/82345 ,  H01L21/823493 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/36 ,  H01L29/66537 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7836

摘要： An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.

摘要翻译： 具有穿通抑制的高级晶体管包括具有长度为Lg的阱，阱掺杂以具有掺杂剂的第一浓度，以及位于栅极下方并具有第二掺杂浓度的屏蔽区域。 掺杂剂的第二浓度可以大于每立方厘米5×1018个掺杂剂原子。 在筛选区域和井之间的栅极下方设置有至少一个穿孔抑制区域。 穿通抑制区域具有在第一浓度和第二浓度掺杂剂之间的掺杂剂的第三浓度。 可以将偏置电压施加到阱区域以调整晶体管的阈值电压。

公开(公告)号：US20090075445A1

公开(公告)日：2009-03-19

申请号：US12313368

申请日：2008-11-19

申请人： Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew V. Metz ,  Suman Datta ,  Brian S. Doyle ,  Robert S. Chau ,  Everett X. Wang ,  Philippe Matagne ,  Lucian Shifren ,  Been Y. Jin ,  Mark Stettler ,  Martin D. Giles

发明人： Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew V. Metz ,  Suman Datta ,  Brian S. Doyle ,  Robert S. Chau ,  Everett X. Wang ,  Philippe Matagne ,  Lucian Shifren ,  Been Y. Jin ,  Mark Stettler ,  Martin D. Giles

IPC分类号： H01L21/336

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848 ,  Y10S438/933

摘要： A transistor may be formed of different layers of silicon germanium, a lowest layer having a graded germanium concentration and upper layers having constant germanium concentrations such that the lowest layer is of the form Si1-xGex. The highest layer may be of the form Si1-yGey on the PMOS side. A source and drain may be formed of epitaxial silicon germanium of the form Si1-zGez on the PMOS side. In some embodiments, x is greater than y and z is greater than x in the PMOS device. Thus, a PMOS device may be formed with both uniaxial compressive stress in the channel direction and in-plane biaxial compressive stress. This combination of stress may result in higher mobility and increased device performance in some cases.

摘要翻译： 晶体管可以由不同的硅锗层形成，具有梯度锗浓度的最低层和具有恒定锗浓度的上层，使得最底层具有Si1-xGex形式。 最高层可以是PMOS侧的Si1-yGey形式。 源极和漏极可以由PMOS侧的Si1-zGez形式的外延硅锗形成。 在一些实施例中，在PMOS器件中，x大于y且z大于x。 因此，PMOS器件可以在沟道方向上具有单轴压应力和面内双轴压应力。 在某些情况下，这种压力的组合可能导致更高的移动性和增加的设备性能。

公开(公告)号：US08963249B1

公开(公告)日：2015-02-24

申请号：US14292806

申请日：2014-05-30

申请人： Lucian Shifren ,  Pushkar Ranade

发明人： Lucian Shifren ,  Pushkar Ranade

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L29/76 ,  H01L29/94 ,  H01L31/0392 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/786

CPC分类号： H01L29/786 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78696

摘要： A field effect transistor having a source, drain, and a gate can include a semiconductor substrate, a buried insulator layer positioned on the semiconductor substrate, and a semiconductor overlayer positioned on the buried insulator layer; a low dopant channel region positioned below the gate and between the source and the drain and in an upper portion of the semiconductor overlayer; and a plurality of doped regions having a predetermined dopant concentration profile, including a screening region positioned in the semiconductor overlayer below the low dopant channel region, the screening region extending toward the buried insulator layer, and a threshold voltage set region positioned between the screening region and the low dopant channel, the screening region and the threshold voltage set region having each a peak dopant concentration, the threshold voltage region peak dopant concentration being between 1/50 and ½ of the peak dopant concentration of the screening region.

摘要翻译： 具有源极，漏极和栅极的场效应晶体管可以包括半导体衬底，位于半导体衬底上的掩埋绝缘体层和位于掩埋绝缘体层上的半导体覆层; 位于栅极下方以及源极和漏极之间以及位于半导体覆盖层的上部的低掺杂剂沟道区; 以及具有预定掺杂剂浓度分布的多个掺杂区域，包括位于低掺杂剂沟道区域之下的半导体覆盖层中的屏蔽区域，朝向掩埋绝缘体层延伸的屏蔽区域，以及位于屏蔽区域之间的阈值电压设置区域 和低掺杂剂通道，筛选区域和阈值电压设置区域各自具有峰值掺杂剂浓度，阈值电压区域峰值掺杂剂浓度在筛选区域的峰值掺杂剂浓度的1/50和1/2之间。