公开(公告)号：US20100109046A1

公开(公告)日：2010-05-06

申请号：US12290809

申请日：2008-11-03

申请人： Rishabh Mehandru ,  Bernhard Sell ,  Anand Murthy ,  Lucian Shifren

发明人： Rishabh Mehandru ,  Bernhard Sell ,  Anand Murthy ,  Lucian Shifren

IPC分类号： H01L29/778 ,  H01L21/336

CPC分类号： H01L21/26513 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/76804 ,  H01L21/76814 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7834

摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a tapered contact opening in an ILD disposed on a substrate, wherein a source/drain contact area is exposed, preamorphizing a portion of a source drain region of the substrate, implanting boron into the source/drain region through the tapered contact opening, forming a metal layer on the source/drain contact area, and then annealing the metal layer to form a metal silicide.

摘要翻译： 描述形成微电子器件的方法和相关结构。 这些方法可以包括在设置在衬底上的ILD中形成锥形接触开口，其中暴露源极/漏极接触区域，对基底的源极漏极区域的一部分进行预变质，通过锥形 接触开口，在源极/漏极接触区域上形成金属层，然后退火金属层以形成金属硅化物。

公开(公告)号：US20200098921A1

公开(公告)日：2020-03-26

申请号：US16143222

申请日：2018-09-26

申请人： Willy RACHMADY ,  Patrick MORROW ,  Aaron LILAK ,  Rishabh MEHANDRU ,  Cheng-Ying HUANG ,  Gilbert DEWEY ,  Kimin JUN ,  Ryan KEECH ,  Anh PHAN ,  Ehren MANNEBACH

发明人： Willy RACHMADY ,  Patrick MORROW ,  Aaron LILAK ,  Rishabh MEHANDRU ,  Cheng-Ying HUANG ,  Gilbert DEWEY ,  Kimin JUN ,  Ryan KEECH ,  Anh PHAN ,  Ehren MANNEBACH

IPC分类号： H01L29/78 ,  H01L21/768 ,  H01L29/06 ,  H01L29/66

摘要： Embodiments include transistor devices and a method of forming the transistor devices. A transistor device includes a first dielectric over a substrate, and vias on a first metal layer, where the first metal layer is on an etch stop layer that is on the first dielectric. The transistor device also includes a second dielectric over the first metal layer, vias, and etch stop layer, where the vias include sidewalls, top surfaces, and bottom surfaces, and stacked transistors on the second dielectric and the top surfaces of the vias, where the sidewalls and top surfaces of the vias are positioned within a footprint of the stacked transistors. The stacked transistors include gate electrodes and first and second transistor layers. The first metal layer includes conductive materials including tungsten or cobalt. The footprint may include a bottom surface of the first transistor layer and a bottom surface of the gate electrodes.

公开(公告)号：US20210057413A1

公开(公告)日：2021-02-25

申请号：US16954126

申请日：2018-03-28

申请人： Gilbert DEWEY ,  Ravi PILLARISETTY ,  Jack T. KAVALIEROS ,  Aaron D. LILAK ,  Willy RACHMADY ,  Rishabh MEHANDRU ,  Kimin JUN ,  Anh PHAN ,  Hui Jae YOO ,  Patrick MORROW ,  Cheng-Ying HUANG ,  Matthew V. METZ ,  Intel Corporation

发明人： Gilbert DEWEY ,  Ravi PILLARISETTY ,  Jack T. KAVALIEROS ,  Aaron D. LILAK ,  Willy RACHMADY ,  Rishabh MEHANDRU ,  Kimin JUN ,  Anh PHAN ,  Hui Jae YOO ,  Patrick MORROW ,  Cheng-Ying HUANG ,  Matthew V. METZ

IPC分类号： H01L27/092 ,  H01L21/822 ,  H01L29/08 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/06 ,  H01L29/66 ,  H01L29/06

摘要： An integrated circuit structure comprises a lower device layer that includes a first structure comprising a plurality of PMOS transistors. An upper device layer is formed on the lower device layer, wherein the upper device layer includes a second structure comprising a plurality of NMOS transistors having a group III-V material source/drain region.

公开(公告)号：US20200006575A1

公开(公告)日：2020-01-02

申请号：US16024682

申请日：2018-06-29

申请人： Gilbert DEWEY ,  Aaron LILAK ,  Van H. LE ,  Abhishek A. SHARMA ,  Tahir GHANI ,  Willy RACHMADY ,  Rishabh MEHANDRU ,  Nazila HARATIPOUR ,  Jack T. KAVALIEROS ,  Benjamin CHU-KUNG ,  Seung Hoon SUNG ,  Shriram SHIVARAMAN

发明人： Gilbert DEWEY ,  Aaron LILAK ,  Van H. LE ,  Abhishek A. SHARMA ,  Tahir GHANI ,  Willy RACHMADY ,  Rishabh MEHANDRU ,  Nazila HARATIPOUR ,  Jack T. KAVALIEROS ,  Benjamin CHU-KUNG ,  Seung Hoon SUNG ,  Shriram SHIVARAMAN

IPC分类号： H01L29/786 ,  H01L29/66

摘要： Thin film transistors having U-shaped features are described. In an example, integrated circuit structure including a gate electrode above a substrate, the gate electrode having a trench therein. A channel material layer is over the gate electrode and in the trench, the channel material layer conformal with the trench. A first source or drain contact is coupled to the channel material layer at a first end of the channel material layer outside of the trench. A second source or drain contact is coupled to the channel material layer at a second end of the channel material layer outside of the trench.

公开(公告)号：US20090302398A1

公开(公告)日：2009-12-10

申请号：US12157556

申请日：2008-06-10

申请人： Bernhard Sell ,  Rishabh Mehandru

发明人： Bernhard Sell ,  Rishabh Mehandru

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L29/7834 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/66621

摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may comprise forming a transistor comprising a metal gate disposed on a gate dielectric that is disposed on a substrate, and a source/drain region disposed adjacent a channel region of the transistor. The source/drain region comprises a source/drain extension comprising a vertex point, wherein a top surface of the channel region is substantially planar with the vertex point.

摘要翻译： 描述形成微电子器件的方法和相关结构。 这些方法可以包括形成包括设置在设置在衬底上的栅极电介质上的金属栅极的晶体管，以及邻近晶体管的沟道区域设置的源极/漏极区域。 源极/漏极区域包括源极/漏极延伸部分，其包括顶点，其中沟道区域的顶表面与顶点基本上是平面的。

公开(公告)号：US20120068180A1

公开(公告)日：2012-03-22

申请号：US13292865

申请日：2011-11-09

申请人： Rishabh Mehandru ,  Bernhard Sell ,  Anand Murthy ,  Lucian Shifren

发明人： Rishabh Mehandru ,  Bernhard Sell ,  Anand Murthy ,  Lucian Shifren

IPC分类号： H01L29/78

CPC分类号： H01L21/26513 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/76804 ,  H01L21/76814 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7834

摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a tapered contact opening in an ILD disposed on a substrate, wherein a source/drain contact area is exposed, preamorphizing a portion of a source drain region of the substrate, implanting boron into the source/drain region through the tapered contact opening, forming a metal layer on the source/drain contact area, and then annealing the metal layer to form a metal silicide.

摘要翻译： 描述形成微电子器件的方法和相关结构。 这些方法可以包括在设置在衬底上的ILD中形成锥形接触开口，其中暴露源极/漏极接触区域，对基底的源极漏极区域的一部分进行预变质，通过锥形 接触开口，在源极/漏极接触区域上形成金属层，然后退火金属层以形成金属硅化物。

公开(公告)号：US20110147840A1

公开(公告)日：2011-06-23

申请号：US12646651

申请日：2009-12-23

申请人： Stephen M. Cea ,  Rishabh Mehandru ,  Lucian Shifren ,  Kelin Kuhn

发明人： Stephen M. Cea ,  Rishabh Mehandru ,  Lucian Shifren ,  Kelin Kuhn

IPC分类号： H01L27/12 ,  H01L21/86

CPC分类号： H01L29/785 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7848 ,  H01L2029/7858

摘要： A semiconductor device comprises a substrate and a semiconductor body formed on the substrate. The semiconductor body comprises a source region; and a drain region. The source region or the drain region, or combinations thereof, comprises a first side surface, a second side surface, and a top surface. The first side surface is opposite the second side surface, the top surface is opposite the bottom surface. The source region or the drain region, or combinations thereof, comprise a metal layer formed on the substantially all of the first side surface, substantially all of the second side surface, and the top surface.

摘要翻译： 半导体器件包括形成在衬底上的衬底和半导体本体。 半导体主体包括源极区域; 和漏区。 源区或漏区，或其组合包括第一侧表面，第二侧表面和顶表面。 第一侧表面与第二侧表面相对，顶表面与底表面相对。 源极区域或漏极区域或其组合包括形成在基本上所有第一侧表面上的基本上所有的第二侧表面和顶表面上的金属层。

公开(公告)号：US20190259699A1

公开(公告)日：2019-08-22

申请号：US16348116

申请日：2016-12-23

申请人： Patrick Morrow ,  Mauro J. Kobrinsky ,  Mark T. Bohr ,  Tahir Ghani ,  Rishabh Mehandru

发明人： Patrick Morrow ,  Mauro J. Kobrinsky ,  Mark T. Bohr ,  Tahir Ghani ,  Rishabh Mehandru

IPC分类号： H01L23/528 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L21/306 ,  H01L27/088 ,  H01L27/02 ,  H01L21/8234

摘要： Transistor cell architectures including both front-side and back-side structures. A transistor may include one or more semiconductor fins with a gate stack disposed along a sidewall of a channel portion of the fin. One or more source/drain regions of the fin are etched to form recesses with a depth below the channel region. The recesses may extend through the entire fin height. Source/drain semiconductor is then deposited within the recess, coupling the channel region to a deep source/drain. A back-side of the transistor is processed to reveal the deep source/drain semiconductor material. One or more back-side interconnect metallization levels may couple to the deep source/drain of the transistor.

公开(公告)号：US20110147804A1

公开(公告)日：2011-06-23

申请号：US12646673

申请日：2009-12-23

申请人： Rishabh Mehandru ,  Cory E. Weber ,  Ashutosh Ashutosh ,  Jack Hwang

发明人： Rishabh Mehandru ,  Cory E. Weber ,  Ashutosh Ashutosh ,  Jack Hwang

IPC分类号： H01L29/78 ,  H01L21/20

CPC分类号： H01L29/7845 ,  H01L21/3215 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor device comprises a fin and a metal gate film. The fin is formed on a surface of a semiconductor material. The metal gate film formed on the fin and comprises ions implanted in the metal gate film to form a compressive stress within the metal gate. In one exemplary embodiment, the surface of the semiconductor material comprises a (100) crystalline lattice orientation, and an orientation of the fin is along a direction with respect to the crystalline lattice of the semiconductor. In another exemplary embodiment, the surface of the semiconductor material comprises a (100) crystalline lattice orientation, and the orientation of the fin is along a direction with respect to the crystalline lattice of the semiconductor. The fin comprises an out-of-plane compression that is generated by the compressive stress within the metal gate film.

摘要翻译： 半导体器件包括翅片和金属栅极膜。 翅片形成在半导体材料的表面上。 金属栅极膜形成在翅片上并且包括注入金属栅极膜中的离子，以在金属栅极内形成压应力。 在一个示例性实施例中，半导体材料的表面包括（100）晶格取向，并且鳍的取向相对于半导体的晶格沿着<100>方向。 在另一个示例性实施例中，半导体材料的表面包括（100）晶格取向，鳍的取向相对于半导体的晶格沿着<110>方向。 翅片包括由金属栅膜内的压应力产生的平面外压缩。

公开(公告)号：US07943992B2

公开(公告)日：2011-05-17

申请号：US12157556

申请日：2008-06-10

申请人： Bernhard Sell ,  Rishabh Mehandru

发明人： Bernhard Sell ,  Rishabh Mehandru

IPC分类号： H01L29/76

CPC分类号： H01L29/7834 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/66621

摘要： Methods and associated structures of forming a microelectronic device are described. Those structures may comprise a transistor comprising a metal gate disposed on a gate dielectric that is disposed on a substrate, and a source/drain region disposed adjacent a channel region of the transistor. The source/drain region comprises a source/drain extension comprising a vertex point, wherein a top surface of the channel region is substantially planar with the vertex point.

摘要翻译： 描述形成微电子器件的方法和相关结构。 这些结构可以包括晶体管，其包括设置在基板上的栅极电介质上的金属栅极和与晶体管的沟道区域相邻设置的源极/漏极区域。 源极/漏极区域包括源极/漏极延伸部分，其包括顶点，其中沟道区域的顶表面与顶点基本上是平面的。