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55 条记录 (耗时 0.034 秒)

    Embedded capacitor assembly in a package
    21.
    发明授权
    Embedded capacitor assembly in a package 有权
    嵌入式电容器组装在一个封装中

    公开(公告)号：US06346743B1

    公开(公告)日：2002-02-12

    申请号：US09606531

    申请日：2000-06-30

    申请人： David G. Figueroa ,  Yuan-Liang Li ,  Chee-Yee Chung

    发明人： David G. Figueroa ,  Yuan-Liang Li ,  Chee-Yee Chung

    IPC分类号： H01L2312

    CPC分类号： H05K1/0231 ,  H01L23/642 ,  H01L2224/16225 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/185 ,  Y10S257/916

    摘要： A capacitor assembly having one or more capacitors embedded in the core layer of a package having integrated circuits (ICs) mounted thereon. Each embedded capacitor has plural pairs of first and second electrodes and the package core layer has plural sets of first and second vias dispersed over the pairs of electrodes and being connected thereto. A metal layer is provided on the core layer and includes a first portion having at least one metal strip and a second portion, electrically isolated from each strip. Each metal strip is positioned such that it is extended to overlie both the first electrode of a distinct pair of electrodes and the second electrode of an adjacent, succeeding pair of electrodes and effects a mutual electrical connection between them through first and second vias associated therewith, respectively. A wiring layer which may be a dielectric interlevel connection layer, provided on the metal layer, has plural sets of third vias that are disposed over the center of the capacitor such that adjacently disposed sets of third vias alternate between contacting the individual ones of the metal strips and contacting the second portion of the metal layer to provide interlayer electrical connections therethrough, respectively, to wirings or terminals in the package. The individual metal strips associated with the first portion of the metal layer are to be applied with one of the power and ground reference signals of the package assembly and the second portion thereof is to be applied with the other one of the power and ground voltages. These capacitors may be employed as bypass capacitors in a package assembly for integrated circuits.

    摘要翻译： 一种电容器组件，其具有一个或多个电容器，该电容器嵌入在其上安装有集成电路（IC）的封装的芯层中。 每个嵌入式电容器具有多对第一和第二电极，并且封装芯层具有分散在该对电极上并与之连接的多组第一和第二通孔。 金属层设置在芯层上，并且包括具有至少一个金属带的第一部分和与每个条带电隔离的第二部分。 每个金属条被定位成使得其延伸以覆盖不同对电极的第一电极和相邻的后一对电极的第二电极，并且通过与其相关联的第一和第二通孔来实现它们之间的相互电连接， 分别。 可以是设置在金属层上的电介质层间连接层的布线层具有多个设置在电容器的中心上方的第三通孔，使得相邻设置的第三通孔组在接触金属的各个之间交替 剥离并接触金属层的第二部分以分别提供到包装中的布线或端子的夹层电连接。 与金属层的第一部分相关联的单个金属带将被施加到封装组件的电源和接地参考信号中的一个，并且其第二部分将被施加电源和接地电压中的另一个。 这些电容器可以用作用于集成电路的封装组件中的旁路电容器。

    Socket with low inductance side contacts for a microelectronic device package
    24.
    发明授权
    Socket with low inductance side contacts for a microelectronic device package 失效
    具有用于微电子器件封装的低电感侧触点的插座

    公开(公告)号：US06680526B2

    公开(公告)日：2004-01-20

    申请号：US10125000

    申请日：2002-04-17

    申请人： David G. Figueroa ,  Yuan-Liang Li

    发明人： David G. Figueroa ,  Yuan-Liang Li

    IPC分类号： H01L2348

    CPC分类号： H01L23/50 ,  H01L23/49805 ,  H01L2224/16225 ,  H01R13/24

    摘要： A socket coupled to a circuit board to receive a package of microelectronic device has one or more electrical contacts coupled to its outer surfaces. Each contact provides a low inductance shunt connection from the side of the package to the circuit board. The contact includes multiple adjacent, electrically conductive members, each including a rigid portion and a flexible portion projecting from the rigid portion. The flexible portion is positioned to be in physical contact with a corresponding electrical conductor on an outer surface of the package when the package is coupled to the socket. At least one adjacent pair of the electrically conductive members conduct current in opposite directions to provide mutual inductance. The contact further includes a dielectric layer sandwiched between each two adjacent rigid portions of the conductive members.

    摘要翻译： 耦合到电路板以接收微电子器件封装的插座具有联接到其外表面的一个或多个电触点。 每个触点提供从封装侧到电路板的低电感分流连接。 触点包括多个相邻的导电构件，每个包括刚性部分和从刚性部分突出的柔性部分。 当包装件与插座连接时，柔性部分定位成与包装外表面上的对应电导体物理接触。 至少一对相邻的导电构件在相反方向上传导电流以提供互感。 触点还包括夹在导电构件的每两个相邻的刚性部分之间的电介质层。

    Interconnected series of plated through hole vias and method of fabrication therefor
    25.
    发明授权
    Interconnected series of plated through hole vias and method of fabrication therefor 有权
    互连的电镀通孔通孔及其制造方法

    公开(公告)号：US06493861B1

    公开(公告)日：2002-12-10

    申请号：US09473353

    申请日：1999-12-28

    申请人： Yuan-Liang Li ,  David G. Figueroa

    发明人： Yuan-Liang Li ,  David G. Figueroa

    IPC分类号： G06F1750

    CPC分类号： H01F17/0033 ,  H01F41/041 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15312 ,  H05K1/115 ,  H05K1/165 ,  H05K3/06 ,  H05K3/42 ,  H05K2201/086 ,  H05K2201/097 ,  H05K2201/1006 ,  H05K2203/0723 ,  H01L2224/0401

    摘要： A series of plated through hole (PTH) vias are interconnected by traces that alternate between a top surface and a bottom surface of a dielectric board. The PTH vias in the series can be positioned to create a collinear inductive filter, a coil-type inductive filter, or a transformer. Multiple, electrically isolated series of interconnected PTH vias can be used as a multi-phase inductive filter in one embodiment. In another embodiment, multiple series of interconnected PTH vias are electrically connected by a linking portion of conductive material, resulting in a low-resistance inductive filter. Ferromagnetic material patterns can be embedded in the dielectric board to enhance the inductive characteristics of the interconnected via structures. In one embodiment, a closed-end pattern is provided with two series of interconnected vias coiling around the pattern, resulting in an embedded transformer structure. A method of producing an interconnected series of PTH vias includes providing a dielectric board having a series of holes. In some embodiments, the board includes an embedded ferromagnetic material pattern. The holes and the top and bottom surface of the dielectric board have a conductive material thereupon. Portions of the conductive material are selectively removed, resulting in the embedded inductive filter and/or transformer structure.

    摘要翻译： 一系列电镀通孔（PTH）通孔在电介质板的顶表面和底表面之间交替的迹线互连。 该系列中的PTH通孔可以定位成产生共线感应滤波器，线圈型感应滤波器或变压器。 在一个实施例中，多个电隔离的互连PTH通孔系列可用作多相感应滤波器。 在另一个实施例中，多个互连的PTH通孔系列通过导电材料的连接部分电连接，导致低电阻感应滤波器。 铁磁材料图案可以嵌入电介质板中以增强互连通孔结构的感应特性。 在一个实施例中，闭合端图案具有围绕图案卷绕的两系列互连的通孔，从而形成嵌入式变压器结构。 制造互连的PTH通孔系列的方法包括提供具有一系列孔的电介质板。 在一些实施例中，板包括嵌入的铁磁材料图案。 电介质板的孔和顶表面和底表面具有导电材料。 选择性地去除导电材料的部分，从而产生嵌入的感应滤波器和/或变压器结构。

    Dual-socket interposer and method of fabrication therefor
    26.
    发明授权
    Dual-socket interposer and method of fabrication therefor 失效
    双插座插入器及其制造方法

    公开(公告)号：US06469908B2

    公开(公告)日：2002-10-22

    申请号：US10076893

    申请日：2002-02-14

    申请人： P. R. Patel ,  Yuan-Liang Li ,  David G. Figueroa ,  Shamala Chickamenahalli ,  Huong T. Do

    发明人： P. R. Patel ,  Yuan-Liang Li ,  David G. Figueroa ,  Shamala Chickamenahalli ,  Huong T. Do

    IPC分类号： H05K710

    CPC分类号： H05K1/141 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/15192 ,  H05K1/0262 ,  H05K3/368 ,  H05K7/1092 ,  H05K2201/049 ,  H05K2201/10196 ,  H05K2201/10325 ,  H05K2201/10689 ,  H05K2201/10704 ,  H01L2224/0401

    摘要： An interposer includes two separate sets of pins, and inserts into two sockets on a printed circuit board. One set of pins supplies power to a step down converter (SDC) mounted on the interposer. The second set of pins provide inputs and outputs to an integrated circuit mounted on the interposer. One or more conductive traces in or on the interposer electrically connect an output of the SDC to an input of the integrated circuit, thus supplying regulated power to the integrated circuit through the interposer. The SDC and integrated circuit can be directly mounted on the interposer, or either or both can be mounted on packages that connect to the interposer. The SDC and integrated circuit can be flip chips or can be connected to the interposer or package using wirebonds. The packages can be pinned or connectable by solder bumps.

    摘要翻译： 插入器包括两组独立的引脚，并插入到印刷电路板上的两个插槽中。 一组引脚为安装在插入器上的降压转换器（SDC）供电。 第二组引脚为安装在插入器上的集成电路提供输入和输出。 插入器中或之上的一个或多个导电迹线将SDC的输出电连接到集成电路的输入，从而通过插入器向集成电路提供稳压电力。 SDC和集成电路可以直接安装在插入器上，或者两者都可以安装在连接到插入器的封装上。 SDC和集成电路可以是倒装芯片，也可以使用引线连接到插入器或封装。 封装可以通过焊料凸块固定或连接。

    Universal capacitor terminal design
    30.
    发明授权
    Universal capacitor terminal design 失效
    通用电容端子设计

    公开(公告)号：US06519134B1

    公开(公告)日：2003-02-11

    申请号：US09619088

    申请日：2000-07-19

    申请人： Yuan-Liang Li ,  David G. Figueroa

    发明人： Yuan-Liang Li ,  David G. Figueroa

    IPC分类号： H01G4228

    CPC分类号： H01G4/232

    摘要： A design for capacitor terminals that includes connections to lowermost power and ground plates located within the bottom perimeter of the capacitor itself, for reducing loop inductance. The capacitor is particularly useful in combination with a circuit board, and especially in the power delivery system for a microprocessor.

    摘要翻译： 电容器端子的设计，包括连接到位于电容器本身的底部周边内的最低功率和接地板，以减少环路电感。 电容器特别适用于电路板，特别是在用于微处理器的电力输送系统中。