公开(公告)号：US6127227A

公开(公告)日：2000-10-03

申请号：US236491

申请日：1999-01-25

申请人： Chrong Jung Lin ,  Jong Chen ,  Hung-Der Su ,  Di-Son Kuo

发明人： Chrong Jung Lin ,  Jong Chen ,  Hung-Der Su ,  Di-Son Kuo

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L21/8247

CPC分类号： H01L21/28211 ,  H01L21/28273 ,  H01L29/511

摘要： A method of forming a flash memory cell is disclosed where nitrogen treatment or implantation is employed. Nitrogen introduced into the upper layers of the polysilicon of the floating gate is instrumental in forming an unusually thin layer comprising nitrogen-oxygen-silicon. This N--O--Si layer is formed while growing the bottom oxide layer of the oxide-nitride-oxide, or ONO, the intergate layer between the floating gate and the control gate of the flash memory cell. Nitrogen in the first polysilicon layer provides control for the thickness of the bottom oxide while at the same time suppressing the gradual gate oxidation (GGO) effect in the floating gate. The now augmented ONO composite through the N--O--Si layer provides an enhanced intergate dielectric and hence, a flash memory cell with more precise coupling ratio and better performance.

摘要翻译： 公开了一种形成闪存单元的方法，其中采用氮气处理或植入。 引入浮栅的多晶硅的上层的氮有助于形成包含氮 - 氧 - 硅的异常薄的层。 在生长氧化物 - 氮化物 - 氧化物的底部氧化物层（ONO）的同时，在浮动栅极和闪存单元的控制栅极之间形成栅极层，形成N-O-Si层。 第一多晶硅层中的氮提供对底部氧化物的厚度的控制，同时抑制浮动栅极中的逐渐栅极氧化（GGO）效应。 现在通过N-O-Si层增强的ONO复合材料提供增强的隔间电介质，因此提供具有更精确的耦合比和更好性能的闪存单元。

公开(公告)号：US09245746B2

公开(公告)日：2016-01-26

申请号：US14048971

申请日：2013-10-08

申请人： Hung-Der Su ,  Chien-Wei Chiu ,  Tsung-Yi Huang

发明人： Hung-Der Su ,  Chien-Wei Chiu ,  Tsung-Yi Huang

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/12

CPC分类号： H01L29/205 ,  H01L21/02378 ,  H01L21/0242 ,  H01L21/0254 ,  H01L21/02664 ,  H01L21/30612 ,  H01L29/12 ,  H01L29/2003 ,  H01L29/7845 ,  H01L29/7849

摘要： The present invention discloses a semiconductor composite film with a heterojunction and a manufacturing method thereof. The semiconductor composite film includes: a semiconductor substrate; and a semiconductor epitaxial layer, which is formed on the semiconductor substrate, and it has a first surface and a second surface opposite to each other, wherein the heterojunction is formed between the first surface and the semiconductor substrate, and wherein the semiconductor epitaxial layer further includes at least one recess, which is formed by etching the semiconductor epitaxial layer from the second surface toward the first surface. The recess is for mitigating a strain in the semiconductor composite film.

摘要翻译： 本发明公开了一种具有异质结的半导体复合膜及其制造方法。 半导体复合膜包括：半导体衬底; 以及半导体外延层，其形成在所述半导体基板上，并且具有彼此相对的第一表面和第二表面，其中所述异质结形成在所述第一表面和所述半导体基板之间，并且其中所述半导体外延层进一步 包括通过从第二表面朝向第一表面蚀刻半导体外延层而形成的至少一个凹部。 该凹槽用于减轻半导体复合膜中的应变。

公开(公告)号：US08729630B1

公开(公告)日：2014-05-20

申请号：US14146512

申请日：2014-01-02

申请人： Ching-Yao Yang ,  Tsung-Yi Huang ,  Huan-Ping Chu ,  Hung-Der Su

发明人： Ching-Yao Yang ,  Tsung-Yi Huang ,  Huan-Ping Chu ,  Hung-Der Su

IPC分类号： H01L29/66

CPC分类号： H01L29/4238 ,  H01L21/28114 ,  H01L21/823425 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.

公开(公告)号：US20120187483A1

公开(公告)日：2012-07-26

申请号：US13066622

申请日：2011-04-20

申请人： Ching-Yao Yang ,  Tsung-Yi Huang ,  Huan-Ping Chu ,  Hung-Der Su

发明人： Ching-Yao Yang ,  Tsung-Yi Huang ,  Huan-Ping Chu ,  Hung-Der Su

IPC分类号： H01L29/78 ,  H01L21/8232 ,  H01L21/336

CPC分类号： H01L29/4238 ,  H01L21/28114 ,  H01L21/823425 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.

摘要翻译： 本发明公开了一种双扩散金属氧化物半导体（DMOS）器件及其制造方法。 DMOS设备包括：用于定义设备区域的隔离结构; 具有环形结构的门; 位于环外的排水沟; 以及位于环内的轻掺杂漏极，源极和体电极。 为了增加栅极角落处的次阈值电压，角部完全位于隔离结构上，或者轻掺杂漏极与角分开预定距离。

公开(公告)号：US07838902B2

公开(公告)日：2010-11-23

申请号：US12385721

申请日：2009-04-17

申请人： Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

发明人： Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

IPC分类号： H01L29/74 ,  H01L31/111

CPC分类号： H01L27/098 ,  H01L27/0744 ,  H01L29/7722 ,  H01L29/8083

摘要： A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

公开(公告)号：US20090117696A1

公开(公告)日：2009-05-07

申请号：US12318065

申请日：2008-12-22

申请人： Hung-Der Su

发明人： Hung-Der Su

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L29/7881 ,  H01L27/11558 ,  H01L29/66825

摘要： A fully logic process compatible non-volatile memory cell has a well on a substrate, a pair of source and drain outside the well, a channel between the source and drain, a control gate in the well, and a floating gate having a first portion above the channel, and a second portion above the well. The control gate includes two regions having opposite conductivity types and a third region between the two regions and under the second portion of the floating gate, and thus eliminates the parasitic depletion capacitor in the coupling path of the cell, thereby improving the coupling ratio.

摘要翻译： 完全逻辑工艺兼容的非易失性存储单元在衬底上具有良好的阱，阱外的一对源极和漏极，源极和漏极之间的沟道，阱中的控制栅极以及具有第一部分的浮动栅极 在通道上方，以及井上方的第二部分。 控制栅极包括具有相反导电类型的两个区域和位于两个区域之间的第三区域，并且在浮置栅极的第二部分之下，从而消除了电池耦合路径中的寄生耗尽电容器，从而提高了耦合比。

公开(公告)号：US20090066399A1

公开(公告)日：2009-03-12

申请号：US12230953

申请日：2008-09-09

申请人： An-Tung Chen ,  Li-Wen Fang ,  Hung-Der Su

发明人： An-Tung Chen ,  Li-Wen Fang ,  Hung-Der Su

IPC分类号： H03L5/00

CPC分类号： H03K3/012 ,  H03K3/35613

摘要： A level shift circuit includes an input stage and an output stage coupled to each other by two nodes. The input stage changes the voltages on the nodes according to an input signal, and the output stage determines an output signal according to the voltages on the two nodes. In a transition state, the input stage provides a large current to charge or discharge the first node or the second node so as to quickly change the voltage thereon. In a steady state, the input stage lowers the current so as to reduce power consumption.

摘要翻译： 电平移位电路包括通过两个节点彼此耦合的输入级和输出级。 输入级根据输入信号改变节点上的电压，输出级根据两个节点上的电压来确定输出信号。 在过渡状态下，输入级提供大电流以对第一节点或第二节点进行充电或放电，以便快速地改变其上的电压。 在稳定状态下，输入级降低电流，从而降低功耗。

公开(公告)号：US07382172B2

公开(公告)日：2008-06-03

申请号：US11497587

申请日：2006-08-02

申请人： Pao-Chuan Lin ,  Hung-Der Su ,  An-Tung Chen ,  Jing-Meng Liu

发明人： Pao-Chuan Lin ,  Hung-Der Su ,  An-Tung Chen ,  Jing-Meng Liu

IPC分类号： H03L5/00

CPC分类号： H03K3/35613 ,  H03K3/012

摘要： The present invention discloses a level shift circuit which comprises: level shift means for receiving an input of a first operational voltage and generating an output of a second operational voltage; and a current path connecting with a source of the second operational voltage and providing current to the output of the level shift means to speed up output level switching. The circuit preferably further comprises a power consumption control circuit for stopping excess power consumption when the output of the level shift means has substantially accomplished level switching.

摘要翻译： 本发明公开了一种电平移位电路，包括：电平移位装置，用于接收第一工作电压的输入并产生第二工作电压的输出; 以及与第二工作电压源连接并将电流提供给电平移位装置的输出的电流路径，以加速输出电平切换。 电路优选地还包括功率消耗控制电路，用于在电平移位装置的输出基本上实现电平切换时停止多余的功率消耗。

公开(公告)号：US07327124B2

公开(公告)日：2008-02-05

申请号：US11388158

申请日：2006-03-24

申请人： Jing-Meng Liu ,  Chung-Lung Pai ,  Hung-Der Su ,  Wei-Hsin Wei

发明人： Jing-Meng Liu ,  Chung-Lung Pai ,  Hung-Der Su ,  Wei-Hsin Wei

IPC分类号： G05F1/577

CPC分类号： H02M3/157 ,  H02M3/1588 ,  Y02B70/1466

摘要： A plurality of switches, an inductor and two capacitors are configured to be a boost-inverting converter. To operate the converter in a boost-inverting mode, a control apparatus and method switch the switches such that the inductor is energized in a first phase, the first capacitor is discharged to produce an inverting voltage in a second phase, and the capacitor Cout1 is discharged to produce the inverting voltage and the second capacitor is charged to produce a boost voltage in a third phase. Therefore, the boost-inverting converter has lower peak inductor current and less power loss, and the limitation to the switch design for the boost-inverting converter is relaxed.

摘要翻译： 多个开关，电感器和两个电容器被配置为升压反相转换器。 为了在升压反转模式下操作转换器，控制装置和方法切换开关使得电感器在第一相中通电，第一电容器被放电以产生第二相的反相电压，并且电容器Cout 1 被放电以产生反相电压，并且第二电容器被充电以在第三相中产生升压电压。 因此，升压反相转换器具有较低的峰值电感电流和较小的功率损耗，并且对升压反相转换器的开关设计的限制放宽。

公开(公告)号：US20060109046A1

公开(公告)日：2006-05-25

申请号：US11108742

申请日：2005-04-19

申请人： Chun-Yen Huang ,  Hung-Der Su ,  Jing-Meng Liu ,  Chung-Lung Pai ,  Shih-Hui Chen ,  Yang-Ping Hung

发明人： Chun-Yen Huang ,  Hung-Der Su ,  Jing-Meng Liu ,  Chung-Lung Pai ,  Shih-Hui Chen ,  Yang-Ping Hung

IPC分类号： H03K17/00

CPC分类号： H03K17/0822 ,  H03K3/00 ,  H03K17/00 ,  H03K17/18 ,  H03K17/6871

摘要： A method, which is for determining switching state of a transistor-based switching device that includes a set of transistors, includes the steps of: applying a bias voltage to a transistor having a fastest response so as to dispose the transistors in the set in a desired transistor state; detecting a voltage level at a transistor having a slowest response to the bias voltage; and comparing the detected voltage level with a predetermined threshold voltage level in order to determine the switching state of the switching device. A transistor-based switching device is also disclosed.

摘要翻译： 一种用于确定包括一组晶体管的基于晶体管的开关器件的开关状态的方法包括以下步骤：将偏置电压施加到具有最快响应的晶体管，以将晶体管置于该组中的晶体管中 所需晶体管状态; 检测对所述偏置电压具有最慢响应的晶体管的电压电平; 以及将检测到的电压电平与预定阈值电压电平进行比较，以便确定开关器件的开关状态。 还公开了一种基于晶体管的开关器件。