公开(公告)号：US20170125522A1

公开(公告)日：2017-05-04

申请号：US15403440

申请日：2017-01-11

申请人： Jaesung SIM ,  Youngwoo Park

发明人： Jaesung SIM ,  Youngwoo Park

IPC分类号： H01L29/10 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/788 ,  H01L27/11556 ,  H01L29/267

CPC分类号： H04L49/70 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/267 ,  H01L29/7883 ,  H04L45/16 ,  H04L49/201 ,  H04L49/3009

摘要： Semiconductor memory devices and methods of forming the semiconductor devices may be provided. The semiconductor memory devices may include a channel portion of an active pillar that may be formed of a semiconductor material having a charge mobility greater than a charge mobility of silicon. The semiconductor devices may also include a non-channel portion of the active pillar including a semiconductor material having a high silicon content.

公开(公告)号：US09362303B2

公开(公告)日：2016-06-07

申请号：US14681505

申请日：2015-04-08

申请人： Jaegoo Lee ,  Youngwoo Park ,  Jaeduk Lee

发明人： Jaegoo Lee ,  Youngwoo Park ,  Jaeduk Lee

IPC分类号： H01L29/792 ,  H01L27/115 ,  H01L29/66 ,  H01L21/28 ,  H01L21/768 ,  H01L21/285

CPC分类号： H01L27/11582 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/76877 ,  H01L29/66833 ,  H01L29/7926

摘要： Semiconductor devices are provided including an active pillar protruding from a substrate; a first gate electrode and a second gate electrode adjacent to a sidewall of the active pillar and vertically overlapping with each other, the first and second gate electrodes being insulated from each other; a first intergate insulating layer covering a first surface of the first gate electrode; and a second intergate insulating layer covering a second surface, opposite the first surface, of the second gate electrode and spaced apart from the first intergate insulating layer. The first intergate insulating layer and the second intergate insulating layer define an air gap therebetween.

摘要翻译： 提供半导体器件，其包括从基板突出的有源柱; 与所述有源柱的侧壁相邻并且彼此垂直重叠的第一栅电极和第二栅电极，所述第一栅电极和所述第二栅电极彼此绝缘; 覆盖所述第一栅电极的第一表面的第一隔间绝缘层; 以及覆盖所述第二栅电极的与所述第一表面相对的第二表面并与所述第一栅极绝缘层间隔开的第二栅极绝缘层。 第一隔间绝缘层和第二隔间绝缘层在其间形成气隙。

公开(公告)号：US20150303213A1

公开(公告)日：2015-10-22

申请号：US14644256

申请日：2015-03-11

申请人： Jaesung SIM ,  Youngwoo Park

发明人： Jaesung SIM ,  Youngwoo Park

IPC分类号： H01L27/115 ,  H01L29/267 ,  H01L29/10 ,  H01L29/165 ,  H01L29/788 ,  H01L29/04 ,  H01L29/161

CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L29/1041 ,  H01L29/165 ,  H01L29/267 ,  H01L29/7827

摘要： Semiconductor memory devices and methods of forming the semiconductor devices may be provided. The semiconductor memory devices may include a channel portion of an active pillar that may be formed of a semiconductor material having a charge mobility greater than a charge mobility of silicon. The semiconductor devices may also include a non-channel portion of the active pillar including a semiconductor material having a high silicon content.

摘要翻译： 可以提供半导体存储器件和形成半导体器件的方法。 半导体存储器件可以包括可以由电荷迁移率大于硅的电荷迁移率的半导体材料形成的有源支柱的沟道部分。 半导体器件还可以包括有源柱的非沟道部分，其包括具有高硅含量的半导体材料。

公开(公告)号：US08829589B2

公开(公告)日：2014-09-09

申请号：US13757273

申请日：2013-02-01

申请人： Changhyun Lee ,  Byoungkeun Son ,  Youngwoo Park

发明人： Changhyun Lee ,  Byoungkeun Son ,  Youngwoo Park

IPC分类号： H01L29/788 ,  H01L29/04 ,  H01L29/792

CPC分类号： H01L29/788 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/04 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926

摘要： A three-dimensional semiconductor memory device may include gap-fill insulating layers extending upward from a substrate, an electrode structure delimited by sidewalls of the gap-fill insulating layers, vertical structures provided between adjacent ones of the gap-fill insulating layers to penetrate the electrode structure, and at least one separation pattern extending along the gap-fill insulating layers and penetrating at least a portion of the electrode structure. The separation pattern may include at least one separation semiconductor layer.

摘要翻译： 三维半导体存储器件可以包括从衬底向上延伸的间隙填充绝缘层，由间隙填充绝缘层的侧壁限定的电极结构，设置在相邻的间隙填充绝缘层之间的垂直结构以穿透 电极结构，以及沿间隙填充绝缘层延伸并穿透电极结构的至少一部分的至少一个分离图案。 分离图案可以包括至少一个分离半导体层。

公开(公告)号：US20140197470A1

公开(公告)日：2014-07-17

申请号：US14218091

申请日：2014-03-18

申请人： Jaegoo Lee ,  Youngwoo Park

发明人： Jaegoo Lee ,  Youngwoo Park

IPC分类号： H01L21/768 ,  H01L27/115

CPC分类号： H01L21/76832 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

摘要： A plurality of vertical channels of semiconductor material are formed to extend in a vertical direction through the plurality of insulation layers and the plurality of conductive patterns, a gate insulating layer between the conductive pattern and the vertical channels that insulates the conductive pattern from the vertical channels. Conductive contact regions of the at least two of the conductive patterns are in a stepped configuration. An etch stop layer is positioned on the conductive contact regions, wherein the etch stop layer has a first portion on a first one of the plurality of conductive patterns and has a second portion on a second one of the plurality of conductive patterns, wherein the first portion is of a thickness that is greater than a thickness of the second portion.

摘要翻译： 多个垂直通道的半导体材料形成为沿着垂直方向延伸穿过多个绝缘层和多个导电图案，导电图案和垂直沟道之间的栅极绝缘层将导电图案与垂直沟道绝缘 。 至少两个导电图案的导电接触区域处于阶梯状结构。 蚀刻停止层位于导电接触区域上，其中蚀刻停止层在多个导电图案中的第一个上具有第一部分，并且在多个导电图案中的第二个导电图案上具有第二部分，其中第一部分 部分的厚度大于第二部分的厚度。

公开(公告)号：US08741761B2

公开(公告)日：2014-06-03

申请号：US13165256

申请日：2011-06-21

申请人： Jaegoo Lee ,  Byungkwan You ,  Youngwoo Park ,  Kwang Soo Seol

发明人： Jaegoo Lee ,  Byungkwan You ,  Youngwoo Park ,  Kwang Soo Seol

IPC分类号： H01L23/3205 ,  H01L21/31

CPC分类号： H01L21/3205 ,  H01L27/11578 ,  H01L27/11582

摘要： Methods of manufacturing three-dimensional semiconductor devices that may include forming a first spacer on a sidewall inside a first opening formed in a first stack structure, forming a sacrificial filling pattern on the spacer to fill the first opening, forming a second stack structure including a second opening exposing the sacrificial filling pattern on the first stack structure, forming a second spacer on a sidewall inside the second opening, removing the sacrificial filling pattern and removing the first spacer and the second spacer.

摘要翻译： 制造三维半导体器件的方法，其可以包括在形成在第一堆叠结构中的第一开口内的侧壁上形成第一间隔物，在间隔物上形成牺牲填充图案以填充第一开口，形成第二堆叠结构， 在所述第一堆叠结构上暴露所述牺牲填充图案的第二开口，在所述第二开口内的侧壁上形成第二间隔件，去除所述牺牲填充图案并移除所述第一间隔件和所述第二间隔件。

公开(公告)号：US08704288B2

公开(公告)日：2014-04-22

申请号：US13238319

申请日：2011-09-21

申请人： Jaegoo Lee ,  Youngwoo Park

发明人： Jaegoo Lee ,  Youngwoo Park

IPC分类号： H01L29/788 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/76832 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

摘要： A plurality of vertical channels of semiconductor material are formed to extend in a vertical direction through the plurality of insulation layers and the plurality of conductive patterns, a gate insulating layer between the conductive pattern and the vertical channels that insulates the conductive pattern from the vertical channels. Conductive contact regions of the at least two of the conductive patterns are in a stepped configuration. An etch stop layer is positioned on the conductive contact regions, wherein the etch stop layer has a first portion on a first one of the plurality of conductive patterns and has a second portion on a second one of the plurality of conductive patterns, wherein the first portion is of a thickness that is greater than a thickness of the second portion.

摘要翻译： 多个垂直通道的半导体材料形成为沿着垂直方向延伸穿过多个绝缘层和多个导电图案，导电图案和垂直沟道之间的栅极绝缘层将导电图案与垂直沟道绝缘 。 至少两个导电图案的导电接触区域处于阶梯状结构。 蚀刻停止层位于导电接触区域上，其中蚀刻停止层在多个导电图案中的第一个上具有第一部分，并且在多个导电图案中的第二个导电图案上具有第二部分，其中第一部分 部分的厚度大于第二部分的厚度。

公开(公告)号：US20120052674A1

公开(公告)日：2012-03-01

申请号：US13214462

申请日：2011-08-22

申请人： Jaegoo LEE ,  Youngwoo Park ,  Jungdal Choi

发明人： Jaegoo LEE ,  Youngwoo Park ,  Jungdal Choi

IPC分类号： H01L21/8239

CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/7827 ,  H01L29/7926

摘要： A method of fabricating a semiconductor memory device includes forming a mold stack on a substrate and the mold stack including first sacrificial layers and second sacrificial layers alternately stacked on the substrate. The method also includes forming a plurality of vertical channels that penetrate the mold stack and that contact the substrate, patterning the mold stack to form word line cuts between the vertical channels, the word line cuts exposing the substrate, removing one of the first and second sacrificial layers to form recessed regions in the mold stack, forming a data storage layer, at least a portion of the data storage layer being formed between the vertical channels and the gates, forming gates in the recessed regions, forming air gaps between the gates by removing the other of the first and second sacrificial layers, and forming an insulation layer pattern in the word line cuts.

摘要翻译： 一种制造半导体存储器件的方法包括在衬底上形成模具堆叠，并且模具叠层包括交替层叠在衬底上的第一牺牲层和第二牺牲层。 该方法还包括形成多个垂直通道，其穿过模具叠层并与衬底接触，图案化模具叠层以形成垂直通道之间的字线切口，字线切割暴露衬底，去除第一和第二 牺牲层，以在模具堆叠中形成凹陷区域，形成数据存储层，数据存储层的至少一部分形成在垂直沟道和栅极之间，在凹陷区域中形成栅极，在栅极之间形成气隙，通过 去除第一和第二牺牲层中的另一个，并且在字线切割中形成绝缘层图案。

公开(公告)号：US08822322B2

公开(公告)日：2014-09-02

申请号：US13214462

申请日：2011-08-22

申请人： Jaegoo Lee ,  Youngwoo Park ,  Jungdal Choi

发明人： Jaegoo Lee ,  Youngwoo Park ,  Jungdal Choi

IPC分类号： H01L21/8239

CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/7827 ,  H01L29/7926

摘要： A method of fabricating a semiconductor memory device includes forming a mold stack on a substrate and the mold stack including first sacrificial layers and second sacrificial layers alternately stacked on the substrate. The method also includes forming a plurality of vertical channels that penetrate the mold stack and that contact the substrate, patterning the mold stack to form word line cuts between the vertical channels, the word line cuts exposing the substrate, removing one of the first and second sacrificial layers to form recessed regions in the mold stack, forming a data storage layer, at least a portion of the data storage layer being formed between the vertical channels and the gates, forming gates in the recessed regions, forming air gaps between the gates by removing the other of the first and second sacrificial layers, and forming an insulation layer pattern in the word line cuts.

摘要翻译： 一种制造半导体存储器件的方法包括在衬底上形成模具堆叠，并且模具叠层包括交替层叠在衬底上的第一牺牲层和第二牺牲层。 该方法还包括形成多个垂直通道，其穿过模具叠层并与衬底接触，图案化模具叠层以形成垂直通道之间的字线切口，字线切割暴露衬底，去除第一和第二 牺牲层，以在模具堆叠中形成凹陷区域，形成数据存储层，数据存储层的至少一部分形成在垂直沟道和栅极之间，在凹陷区域中形成栅极，在栅极之间形成气隙，通过 去除第一和第二牺牲层中的另一个，并且在字线切割中形成绝缘层图案。

公开(公告)号：US08643080B2

公开(公告)日：2014-02-04

申请号：US13217416

申请日：2011-08-25

申请人： Changhyun Lee ,  Byoungkeun Son ,  Youngwoo Park

发明人： Changhyun Lee ,  Byoungkeun Son ,  Youngwoo Park

IPC分类号： H01L29/788 ,  H01L29/792 ,  H01L21/06 ,  H01L21/336

CPC分类号： H01L27/11578 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/7889 ,  H01L29/7926

摘要： Provided are three-dimensional semiconductor devices. The devices may include gap-fill insulating patterns configured to upwardly extend from a substrate and an electrode structure defined by sidewalls of the gap-fill insulating patterns. Vertical structures may be provided between adjacent ones of the gap-fill insulating patterns to penetrate the electrode structure, and the vertical structures may include first and second rows of the vertical structures. A separation pattern may be provided between the first and second rows of vertical structures and include a separation semiconductor layer. The separation pattern extends along a direction parallel to the first and second rows of vertical structures.

摘要翻译： 提供三维半导体器件。 这些装置可以包括配置成从基板向上延伸的间隙填充绝缘图案和由间隙填充绝缘图案的侧壁限定的电极结构。 可以在相邻的间隙填充绝缘图案之间提供垂直结构以穿透电极结构，并且垂直结构可以包括垂直结构的第一行和第二行。 可以在第一和第二排垂直结构之间提供分离图案，并且包括分离半导体层。 分离图案沿着平行于第一和第二排垂直结构的方向延伸。