公开(公告)号：US07473986B2

公开(公告)日：2009-01-06

申请号：US11563814

申请日：2006-11-28

申请人： Kern-Huat Ang ,  Ling-Sung Wang

发明人： Kern-Huat Ang ,  Ling-Sung Wang

IPC分类号： H01L29/00

CPC分类号： H01L23/5252 ,  H01L27/1021 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices and fabrication methods thereof. A first dielectric layer with a first conductor line along a first direction is disposed on a semiconductor substrate, wherein the top surface of the first conductor line is lower than the top surface of the first dielectric layer. A second dielectric layer comprising an opening corresponding to the first diode element is disposed on the first dielectric layer. A semiconductor diode component comprises a first diode element disposed on the first conductor line, wherein the top surface of the first diode element is level with the top surface of the first dielectric layer; and a second diode element and a third diode element are filled in the opening.

摘要翻译： 半导体器件及其制造方法。 具有沿着第一方向具有第一导体线的第一电介质层设置在半导体衬底上，其中第一导体线的顶表面比第一电介质层的顶表面低。 包括对应于第一二极管元件的开口的第二电介质层设置在第一电介质层上。 半导体二极管部件包括设置在第一导体线上的第一二极管元件，其中第一二极管元件的顶表面与第一介电层的顶表面平齐; 并且第二二极管元件和第三二极管元件填充在开口中。

公开(公告)号：US06524909B1

公开(公告)日：2003-02-25

申请号：US09494524

申请日：2000-01-31

申请人： Ling-Sung Wang ,  Jyh-Ren Wu

发明人： Ling-Sung Wang ,  Jyh-Ren Wu

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L21/28273

摘要： A self-aligned fabricating process and a structure of ETOX flash memory. A plurality of parallel lines for device isolation is formed in a substrate, and then forming a plurality of parallel stacked gates above the substrate. The device isolation lines and the stacked gates are perpendicular to each other. A plurality of first insulation layers is formed such that an insulation layer is formed over each stacked gate. Spacers are also formed over the sidewalls of each stacked gate. A plurality of source arrays and drain arrays are formed in the substrate between neighboring stacked gates. The source and drain arrays are parallel to the stacked gates, with a source array and a drain array formed in alternating positions between the stacked gates. Each source array comprises a plurality of source-doped regions located between the device isolation lines respectively. Similarly, each drain array has a plurality of drain-doped regions located between the device isolation lines. A plurality of source lines is formed in the space between neighboring spacers above the source array.

摘要翻译： 自对准制造工艺和ETOX闪存的结构。 在衬底中形成用于器件隔离的多条平行线，然后在衬底上形成多个平行的堆叠栅极。 器件隔离线和堆叠栅极彼此垂直。 形成多个第一绝缘层，使得在每个堆叠的栅极上形成绝缘层。 隔板也形成在每个堆叠门的侧壁上。 在相邻堆叠栅极之间的衬底中形成多个源极阵列和漏极阵列。 源极和漏极阵列平行于堆叠栅极，源极阵列和漏极阵列形成在堆叠栅极之间的交替位置。 每个源极阵列分别包括位于器件隔离线之间的多个源极掺杂区域。 类似地，每个漏极阵列具有位于器件隔离线之间的多个漏极掺杂区域。 在源阵列上方的相邻间隔物之间​​的空间中形成多条源极线。

公开(公告)号：US06245667B1

公开(公告)日：2001-06-12

申请号：US09465905

申请日：1999-12-17

申请人： Ling-Sung Wang ,  Chingfu Lin ,  Chien-Jung Wang

发明人： Ling-Sung Wang ,  Chingfu Lin ,  Chien-Jung Wang

IPC分类号： H01L214763

CPC分类号： H01L21/76897 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a via. A stacked structure has a barrier layer and a metal line is formed over a substrate. Spacers capable of serving as a barrier are formed over tapering sidewalls of the stacked structure before vias and plugs are formed.

摘要翻译： 形成通孔的方法。 堆叠结构具有阻挡层，并且在衬底上形成金属线。 在形成通孔和插塞之前，可以在堆叠结构的锥形侧壁上形成能够用作屏障的间隔物。

公开(公告)号：US6146946A

公开(公告)日：2000-11-14

申请号：US417393

申请日：1999-10-13

申请人： Ling-Sung Wang ,  Jyh-Ren Wu

发明人： Ling-Sung Wang ,  Jyh-Ren Wu

IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L29/51 ,  H01L21/336

CPC分类号： H01L29/511 ,  H01L21/28273 ,  H01L29/42324

摘要： The invention describes a method of fabricating an integrated circuit used to prevent undercutting of an oxide layer due to wet etching. A semiconductor substrate has a gate formed thereon. A conformal oxide layer is formed to cover the gate. Then, a nitrogen ion implantation process is performed to introduce nitrogen ions into the surface of the conformal oxide layer. A high temperature thermal oxidation is performed in order to form Si--N bonds, that is, the nitrogen ions bonding with the silicon atoms of the conformal oxide layer, or to form Si--ON bonds, that is, the nitrogen ions bonding with the oxygen atoms of the conformal oxide layer. A dielectric layer, which covers the conformal oxide layer, is formed. Thereafter, the dielectric layer is etched back to form spacers on the sidewalls of the gate. A wet etching process is performed to remove a part of the conformal oxide layer exposed by the spacers.

摘要翻译： 本发明描述了一种制造集成电路的方法，该集成电路用于防止由于湿蚀刻而导致的氧化层的底切。 半导体衬底具有形成在其上的栅极。 形成保形氧化物层以覆盖栅极。 然后，进行氮离子注入工艺以将氮离子引入保形氧化物层的表面。 进行高温热氧化以形成Si-N键，即与保形氧化物层的硅原子结合的氮离子，或者形成Si-ON键，即氮离子与 保形氧化物层的氧原子。 形成覆盖保形氧化物层的电介质层。 此后，电介质层被回蚀以在栅极的侧壁上形成间隔物。 执行湿蚀刻工艺以去除由间隔物暴露的一部分共形氧化物层。

公开(公告)号：US6026028A

公开(公告)日：2000-02-15

申请号：US123305

申请日：1998-07-28

申请人： Chen-Hsi Lin ,  Chih-Ming Chen ,  Ling-Sung Wang ,  Horng-Ming Lee ,  Ko-Hsing Chang

发明人： Chen-Hsi Lin ,  Chih-Ming Chen ,  Ling-Sung Wang ,  Horng-Ming Lee ,  Ko-Hsing Chang

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C13/00

CPC分类号： H01L29/7885

摘要： A flash electrical erasable programmable read only memory structure that utilizes hot carrier injection for programming and negative gate voltage to carry out channel erase operations. Characteristic of the memory structure includes a triple well structure having a P-well and an N-well located within a P-type substrate, wherein the N-well isolated the P-well from the P-type substrate. Therefore, an independently isolated triple well structure is established during memory erase operation.

摘要翻译： 闪存电可擦除可编程只读存储器结构，其利用热载流子注入用于编程和负栅极电压来执行通道擦除操作。 存储器结构的特征包括具有P阱和位于P型衬底内的N阱的三阱结构，其中N阱从P型衬底隔离P阱。 因此，在存储器擦除操作期间建立独立隔离的三重阱结构。

公开(公告)号：US09343318B2

公开(公告)日：2016-05-17

申请号：US13367989

申请日：2012-02-07

申请人： Mei-Hsuan Lin ,  Chih-Hsun Lin ,  Ching-Hua Chu ,  Ling-Sung Wang

发明人： Mei-Hsuan Lin ,  Chih-Hsun Lin ,  Ching-Hua Chu ,  Ling-Sung Wang

IPC分类号： H01L21/285 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/28518 ,  H01L21/02381 ,  H01L21/02425 ,  H01L21/02532 ,  H01L21/02617 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L29/41783 ,  H01L29/4933 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/7845 ,  H01L29/7848

摘要： A semiconductor device having a source feature and a drain feature formed in a substrate. The semiconductor device having a gate stack over a portion of the source feature and over a portion of the drain feature. The semiconductor device further having a first cap layer formed over substantially the entire source feature not covered by the gate stack, and a second cap layer formed over substantially the entire drain feature not covered by the gate stack. A method of forming a semiconductor device including forming a source feature and drain feature in a substrate. The method further includes forming a gate stack over a portion of the source feature and over a portion of the drain feature. The method further includes depositing a first cap layer over substantially the entire source feature not covered by the gate stack and a second cap layer over substantially the entire drain feature not covered by the gate stack.

摘要翻译： 一种半导体器件，其具有形成在衬底中的源特征和漏极特征。 该半导体器件在源特征的一部分上方并且在漏极特征的一部分上方具有栅极堆叠。 所述半导体器件还具有形成在基本上整个源极特征上的第一覆盖层，其未被所述栅极堆叠覆盖，以及形成在基本上整个漏极特征（未被所述栅极堆叠覆盖）的第二覆盖层。 一种形成半导体器件的方法，包括在衬底中形成源极特征和漏极特征。 该方法还包括在源特征的一部分上并在漏极特征的一部分之上形成栅叠层。 该方法还包括在未被栅极堆叠覆盖的基本上整个源特征上沉积第一盖层，以及在未被栅极堆叠覆盖的基本整个漏极特征上沉积第二盖层。

公开(公告)号：US08659089B2

公开(公告)日：2014-02-25

申请号：US13267648

申请日：2011-10-06

申请人： Jia-Yang Ko ,  Ching-Chien Huang ,  Ying-Han Chiou ,  Ling-Sung Wang

发明人： Jia-Yang Ko ,  Ching-Chien Huang ,  Ying-Han Chiou ,  Ling-Sung Wang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/0217 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0653 ,  H01L29/66628 ,  H01L29/66636

摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. In an example, the method includes providing a substrate; forming a gate structure over the substrate; removing portions of the substrate to form a first recess and a second recess in the substrate, such that the gate structure interposes the first recess and the second recess; forming a nitrogen passivation layer in the substrate, such that the first recess and the second recess are defined by nitrogen passivated surfaces of the substrate; and forming doped source and drain features over the nitrogen passivated surfaces of the first recess and the second recess, the doped source and drain features filling the first and second recesses.

摘要翻译： 公开了一种用于制造集成电路器件的集成电路器件和方法。 在一个实例中，该方法包括提供基底; 在衬底上形成栅极结构; 去除所述衬底的部分以在所述衬底中形成第一凹部和第二凹部，使得所述栅极结构将所述第一凹部和所述第二凹部中间; 在所述基板中形成氮钝化层，使得所述第一凹部和所述第二凹部由所述基板的氮钝化表面限定; 以及在所述第一凹部和所述第二凹部的氮钝化表面上形成掺杂源极和漏极特征，所述掺杂源极和漏极特征填充所述第一和第二凹部。

公开(公告)号：US08533639B2

公开(公告)日：2013-09-10

申请号：US13233453

申请日：2011-09-15

申请人： Mei-Hsuan Lin ,  Chih-Chan Lu ,  Chih-Hsun Lin ,  Chih-Kang Chao ,  Ling-Sung Wang ,  Jen-Pan Wang

发明人： Mei-Hsuan Lin ,  Chih-Chan Lu ,  Chih-Hsun Lin ,  Chih-Kang Chao ,  Ling-Sung Wang ,  Jen-Pan Wang

IPC分类号： G06F17/50 ,  H01L25/00 ,  H01L29/788 ,  H01L27/11 ,  H01L27/12 ,  H03K19/00

CPC分类号： G06F17/50 ,  G06F17/5072 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823481 ,  H01L25/00 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/12 ,  H01L29/788 ,  H01L2924/0002 ,  H03K19/00 ,  H01L2924/00

摘要： The present disclosure provides an integrated circuit design method. In an example, a method includes receiving an integrated circuit design layout that includes an active region feature, a contact feature, and an isolation feature, wherein a portion of the active region feature is disposed between the contact feature and the isolation feature; determining whether a thickness of the portion of the active region feature disposed between the contact feature and the isolation feature is less than a threshold value; and modifying the integrated circuit design layout if the thickness is less than the threshold value, wherein the modifying includes adding a supplementary active region feature adjacent to the portion of the active region feature disposed between the contact feature and the isolation feature.

摘要翻译： 本公开提供了一种集成电路设计方法。 在一个示例中，一种方法包括接收包括有源区域特征，接触特征和隔离特征的集成电路设计布局，其中有源区域特征的一部分设置在接触特征和隔离特征之间; 确定布置在接触特征和隔离特征之间的有源区域特征的部分的厚度是否小于阈值; 以及如果所述厚度小于所述阈值，则修改所述集成电路设计布局，其中所述修改包括在所述接触特征与所述隔离特征之间的所述有源区域特征的所述部分附近添加辅助有源区域特征。

公开(公告)号：US20130087857A1

公开(公告)日：2013-04-11

申请号：US13267648

申请日：2011-10-06

申请人： Jia-Yang Ko ,  Ching-Chien Huang ,  Ying-Han Chiou ,  Ling-Sung Wang

发明人： Jia-Yang Ko ,  Ching-Chien Huang ,  Ying-Han Chiou ,  Ling-Sung Wang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/0217 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0653 ,  H01L29/66628 ,  H01L29/66636

摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. In an example, the method includes providing a substrate; forming a gate structure over the substrate; removing portions of the substrate to form a first recess and a second recess in the substrate, such that the gate structure interposes the first recess and the second recess; forming a nitrogen passivation layer in the substrate, such that the first recess and the second recess are defined by nitrogen passivated surfaces of the substrate; and forming doped source and drain features over the nitrogen passivated surfaces of the first recess and the second recess, the doped source and drain features filling the first and second recesses.

摘要翻译： 公开了一种用于制造集成电路器件的集成电路器件和方法。 在一个实例中，该方法包括提供基底; 在衬底上形成栅极结构; 去除所述衬底的部分以在所述衬底中形成第一凹部和第二凹部，使得所述栅极结构将所述第一凹部和所述第二凹部中间; 在所述基板中形成氮钝化层，使得所述第一凹部和所述第二凹部由所述基板的氮钝化表面限定; 以及在所述第一凹部和所述第二凹部的氮钝化表面上形成掺杂源极和漏极特征，所述掺杂源极和漏极特征填充所述第一和第二凹部。

公开(公告)号：US20080073755A1

公开(公告)日：2008-03-27

申请号：US11563814

申请日：2006-11-28

申请人： Kern-Huat Ang ,  Ling-Sung Wang

发明人： Kern-Huat Ang ,  Ling-Sung Wang

IPC分类号： H01L31/00

CPC分类号： H01L23/5252 ,  H01L27/1021 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices and fabrication methods thereof. A first dielectric layer with a first conductor line along a first direction is disposed on a semiconductor substrate, wherein the top surface of the first conductor line is lower than the top surface of the first dielectric layer. A second dielectric layer comprising an opening corresponding to the first diode element is disposed on the first dielectric layer. A semiconductor diode component comprises a first diode element disposed on the first conductor line, wherein the top surface of the first diode element is level with the top surface of the first dielectric layer; and a second diode element and a third diode element are filled in the opening.

摘要翻译： 半导体器件及其制造方法。 具有沿着第一方向具有第一导体线的第一电介质层设置在半导体衬底上，其中第一导体线的顶表面比第一电介质层的顶表面低。 包括对应于第一二极管元件的开口的第二电介质层设置在第一电介质层上。 半导体二极管部件包括设置在第一导体线上的第一二极管元件，其中第一二极管元件的顶表面与第一介电层的顶表面平齐; 并且第二二极管元件和第三二极管元件填充在开口中。