公开(公告)号：US08513143B2

公开(公告)日：2013-08-20

申请号：US13212469

申请日：2011-08-18

申请人： Mei-Hsuan Lin ,  Chih-Hsun Lin ,  Chih-Kang Chao ,  Ling-Sung Wang

发明人： Mei-Hsuan Lin ,  Chih-Hsun Lin ,  Chih-Kang Chao ,  Ling-Sung Wang

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L23/481 ,  H01L21/76802 ,  H01L21/76822 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present application discloses a method of manufacturing a semiconductor structure. According to at least one embodiment, a first etch stop layer is formed over a conductive feature and a substrate, and the conductive feature is positioned over the substrate. A second etch stop layer is formed over the first etch stop layer. A first etch is performed to form an opening in the second etch stop layer, and the opening exposes a portion of the first etch stop layer. A second etch is performed to extend the opening downwardly by removing a portion of the exposed first etch stop layer, and the extended opening exposes a portion of the conductive feature.

摘要翻译： 本申请公开了一种制造半导体结构的方法。 根据至少一个实施例，在导电特征和衬底之上形成第一蚀刻停止层，并且导电特征位于衬底上。 在第一蚀刻停止层上形成第二蚀刻停止层。 执行第一蚀刻以在第二蚀刻停止层中形成开口，并且开口暴露第一蚀刻停止层的一部分。 执行第二蚀刻以通过去除暴露的第一蚀刻停止层的一部分向下延伸开口，并且延伸的开口暴露导电特征的一部分。

公开(公告)号：US09343318B2

公开(公告)日：2016-05-17

申请号：US13367989

申请日：2012-02-07

申请人： Mei-Hsuan Lin ,  Chih-Hsun Lin ,  Ching-Hua Chu ,  Ling-Sung Wang

发明人： Mei-Hsuan Lin ,  Chih-Hsun Lin ,  Ching-Hua Chu ,  Ling-Sung Wang

IPC分类号： H01L21/285 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/28518 ,  H01L21/02381 ,  H01L21/02425 ,  H01L21/02532 ,  H01L21/02617 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L29/41783 ,  H01L29/4933 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/7845 ,  H01L29/7848

摘要： A semiconductor device having a source feature and a drain feature formed in a substrate. The semiconductor device having a gate stack over a portion of the source feature and over a portion of the drain feature. The semiconductor device further having a first cap layer formed over substantially the entire source feature not covered by the gate stack, and a second cap layer formed over substantially the entire drain feature not covered by the gate stack. A method of forming a semiconductor device including forming a source feature and drain feature in a substrate. The method further includes forming a gate stack over a portion of the source feature and over a portion of the drain feature. The method further includes depositing a first cap layer over substantially the entire source feature not covered by the gate stack and a second cap layer over substantially the entire drain feature not covered by the gate stack.

摘要翻译： 一种半导体器件，其具有形成在衬底中的源特征和漏极特征。 该半导体器件在源特征的一部分上方并且在漏极特征的一部分上方具有栅极堆叠。 所述半导体器件还具有形成在基本上整个源极特征上的第一覆盖层，其未被所述栅极堆叠覆盖，以及形成在基本上整个漏极特征（未被所述栅极堆叠覆盖）的第二覆盖层。 一种形成半导体器件的方法，包括在衬底中形成源极特征和漏极特征。 该方法还包括在源特征的一部分上并在漏极特征的一部分之上形成栅叠层。 该方法还包括在未被栅极堆叠覆盖的基本上整个源特征上沉积第一盖层，以及在未被栅极堆叠覆盖的基本整个漏极特征上沉积第二盖层。

公开(公告)号：US08533639B2

公开(公告)日：2013-09-10

申请号：US13233453

申请日：2011-09-15

申请人： Mei-Hsuan Lin ,  Chih-Chan Lu ,  Chih-Hsun Lin ,  Chih-Kang Chao ,  Ling-Sung Wang ,  Jen-Pan Wang

发明人： Mei-Hsuan Lin ,  Chih-Chan Lu ,  Chih-Hsun Lin ,  Chih-Kang Chao ,  Ling-Sung Wang ,  Jen-Pan Wang

IPC分类号： G06F17/50 ,  H01L25/00 ,  H01L29/788 ,  H01L27/11 ,  H01L27/12 ,  H03K19/00

CPC分类号： G06F17/50 ,  G06F17/5072 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823481 ,  H01L25/00 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/12 ,  H01L29/788 ,  H01L2924/0002 ,  H03K19/00 ,  H01L2924/00

摘要： The present disclosure provides an integrated circuit design method. In an example, a method includes receiving an integrated circuit design layout that includes an active region feature, a contact feature, and an isolation feature, wherein a portion of the active region feature is disposed between the contact feature and the isolation feature; determining whether a thickness of the portion of the active region feature disposed between the contact feature and the isolation feature is less than a threshold value; and modifying the integrated circuit design layout if the thickness is less than the threshold value, wherein the modifying includes adding a supplementary active region feature adjacent to the portion of the active region feature disposed between the contact feature and the isolation feature.

摘要翻译： 本公开提供了一种集成电路设计方法。 在一个示例中，一种方法包括接收包括有源区域特征，接触特征和隔离特征的集成电路设计布局，其中有源区域特征的一部分设置在接触特征和隔离特征之间; 确定布置在接触特征和隔离特征之间的有源区域特征的部分的厚度是否小于阈值; 以及如果所述厚度小于所述阈值，则修改所述集成电路设计布局，其中所述修改包括在所述接触特征与所述隔离特征之间的所述有源区域特征的所述部分附近添加辅助有源区域特征。

公开(公告)号：US20130043590A1

公开(公告)日：2013-02-21

申请号：US13212469

申请日：2011-08-18

申请人： Mei-Hsuan LIN ,  Chih-Hsun LIN ,  Chih-Kang CHAO ,  Ling-Sung WANG

发明人： Mei-Hsuan LIN ,  Chih-Hsun LIN ,  Chih-Kang CHAO ,  Ling-Sung WANG

IPC分类号： H01L21/768 ,  H01L23/48

CPC分类号： H01L23/481 ,  H01L21/76802 ,  H01L21/76822 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present application discloses a method of manufacturing a semiconductor structure. According to at least one embodiment, a first etch stop layer is formed over a conductive feature and a substrate, and the conductive feature is positioned over the substrate. A second etch stop layer is formed over the first etch stop layer. A first etch is performed to form an opening in the second etch stop layer, and the opening exposes a portion of the first etch stop layer. A second etch is performed to extend the opening downwardly by removing a portion of the exposed first etch stop layer, and the extended opening exposes a portion of the conductive feature.

摘要翻译： 本申请公开了一种制造半导体结构的方法。 根据至少一个实施例，在导电特征和衬底之上形成第一蚀刻停止层，并且导电特征位于衬底上。 在第一蚀刻停止层上形成第二蚀刻停止层。 执行第一蚀刻以在第二蚀刻停止层中形成开口，并且开口暴露第一蚀刻停止层的一部分。 执行第二蚀刻以通过去除暴露的第一蚀刻停止层的一部分向下延伸开口，并且延伸的开口暴露导电特征的一部分。

公开(公告)号：US08527915B2

公开(公告)日：2013-09-03

申请号：US13286410

申请日：2011-11-01

申请人： Mei-Hsuan Lin ,  Ling-Sung Wang ,  Chih-Hsun Lin ,  Chih-Kang Chao

发明人： Mei-Hsuan Lin ,  Ling-Sung Wang ,  Chih-Hsun Lin ,  Chih-Kang Chao

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  H01L21/26586 ,  H01L29/6659

摘要： The present disclosure provides a method and system for modifying a doped region design layout during mask preparation to tune device performance. An exemplary method includes receiving an integrated circuit design layout designed to define an integrated circuit, wherein the integrated circuit design layout includes a doped feature layout; identifying an area of the integrated circuit for device performance modification, and modifying a portion of the doped feature layout that corresponds with the identified area of the integrated circuit during a mask preparation process, thereby providing a modified doped feature layout.

摘要翻译： 本公开提供了一种用于在掩模准备期间修改掺杂区域设计布局以调谐设备性能的方法和系统。 一种示例性方法包括接收设计成定义集成电路的集成电路设计布局，其中集成电路设计布局包括掺杂特征布局; 识别用于器件性能修改的集成电路的区域，以及在掩模准备过程期间修改与所识别的集成电路的区域相对应的掺杂特征布局的一部分，从而提供修改的掺杂特征布局。

公开(公告)号：US08470660B2

公开(公告)日：2013-06-25

申请号：US13234296

申请日：2011-09-16

申请人： Mei-Hsuan Lin ,  Chih-Kang Chao ,  Chih-Hsun Lin ,  Ling-Sung Wang

发明人： Mei-Hsuan Lin ,  Chih-Kang Chao ,  Chih-Hsun Lin ,  Ling-Sung Wang

IPC分类号： H01L21/8238

CPC分类号： H01L21/8238 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/66636 ,  H01L29/7848

摘要： A method of manufacturing a semiconductor device is disclosed. The exemplary method includes providing a substrate having a source region and a drain region. The method further includes forming a first recess in the substrate within the source region and a second recess in the substrate within the drain region. The first recess has a first plurality of surfaces and the second recess has a second plurality of surfaces. The method also includes epi-growing a semiconductor material in the first and second recesses and, thereafter, forming shallow isolation (STI) features in the substrate.

摘要翻译： 公开了制造半导体器件的方法。 该示例性方法包括提供具有源极区和漏极区的衬底。 该方法还包括在源极区域内的衬底中形成第一凹槽，以及在漏极区域内的衬底中形成第二凹部。 第一凹部具有第一多个表面，第二凹部具有第二多个表面。 该方法还包括在第一和第二凹陷中外延生长半导体材料，然后在衬底中形成浅隔离（STI）特征。

公开(公告)号：US20130071995A1

公开(公告)日：2013-03-21

申请号：US13234296

申请日：2011-09-16

申请人： Mei-Hsuan Lin ,  Chih-Kang Chao ,  Chih-Hsun Lin ,  Ling-Sung Wang

发明人： Mei-Hsuan Lin ,  Chih-Kang Chao ,  Chih-Hsun Lin ,  Ling-Sung Wang

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/8238 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/66636 ,  H01L29/7848

摘要： A method of manufacturing a semiconductor device is disclosed. The exemplary method includes providing a substrate having a source region and a drain region. The method further includes forming a first recess in the substrate within the source region and a second recess in the substrate within the drain region. The first recess has a first plurality of surfaces and the second recess has a second plurality of surfaces. The method also includes epi-growing a semiconductor material in the first and second recesses and, thereafter, forming shallow isolation (STI) features in the substrate.

摘要翻译： 公开了制造半导体器件的方法。 该示例性方法包括提供具有源极区和漏极区的衬底。 该方法还包括在源极区域内的衬底中形成第一凹槽，以及在漏极区域内的衬底中形成第二凹部。 第一凹部具有第一多个表面，第二凹部具有第二多个表面。 该方法还包括在第一和第二凹陷中外延生长半导体材料，然后在衬底中形成浅隔离（STI）特征。

公开(公告)号：US08846492B2

公开(公告)日：2014-09-30

申请号：US13188976

申请日：2011-07-22

申请人： Mei-Hsuan Lin ,  Chih-Hsun Lin ,  Chih-Kang Chao ,  Ling-Sung Wang

发明人： Mei-Hsuan Lin ,  Chih-Hsun Lin ,  Chih-Kang Chao ,  Ling-Sung Wang

IPC分类号： H01L21/76 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L29/0847 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

摘要： An embodiment of the disclosure includes a method of forming a semiconductor structure. A substrate has a region adjacent to a shallow trench isolation (STI) structure in the substrate. A patterned mask layer is formed over the substrate. The patterned mask layer covers the STI structure and a portion of the region, and leaves a remaining portion of the region exposed. A distance between an edge of the remaining portion and an edge of the STI structure is substantially longer than 1 nm. The remaining portion of the region is etched thereby forms a recess in the substrate. A stressor is epitaxially grown in the recess. A conductive plug contacting the stressor is formed.

摘要翻译： 本公开的实施例包括形成半导体结构的方法。 衬底具有与衬底中的浅沟槽隔离（STI）结构相邻的区域。 在衬底上形成图案化掩模层。 图案化掩模层覆盖STI结构和区域的一部分，并且使该区域的剩余部分露出。 剩余部分的边缘与STI结构的边缘之间的距离基本上长于1nm。 蚀刻该区域的剩余部分，从而在该基底中形成凹陷。 应力源在凹槽中外延生长。 形成与应力器接触的导电塞。

公开(公告)号：US20130234217A1

公开(公告)日：2013-09-12

申请号：US13415611

申请日：2012-03-08

申请人： Mei-Hsuan Lin ,  Chih-Hsun Lin ,  Ching-Hua Chu ,  Ling-Sung Wang

发明人： Mei-Hsuan Lin ,  Chih-Hsun Lin ,  Ching-Hua Chu ,  Ling-Sung Wang

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/66507 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/02694 ,  H01L21/30604 ,  H01L21/308 ,  H01L29/165 ,  H01L29/41758 ,  H01L29/45 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A device includes a semiconductor substrate, a gate stack over the semiconductor substrate, and a stressor region having at least a portion in the semiconductor substrate and adjacent to the gate stack. The stressor region includes a first stressor region having a first p-type impurity concentration, a second stressor region over the first stressor region, wherein the second stressor region has a second p-type impurity concentration, and a third stressor region over the second stressor region. The third stressor region has a third p-type impurity concentration. The second p-type impurity concentration is lower than the first and the third p-type impurity concentrations.

公开(公告)号：US20130111419A1

公开(公告)日：2013-05-02

申请号：US13286410

申请日：2011-11-01

申请人： Mei-Hsuan Lin ,  Ling-Sung Wang ,  Chih-Hsun Lin ,  Chih-Kang Chao

发明人： Mei-Hsuan Lin ,  Ling-Sung Wang ,  Chih-Hsun Lin ,  Chih-Kang Chao

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  H01L21/26586 ,  H01L29/6659

摘要： The present disclosure provides a method and system for modifying a doped region design layout during mask preparation to tune device performance. An exemplary method includes receiving an integrated circuit design layout designed to define an integrated circuit, wherein the integrated circuit design layout includes a doped feature layout; identifying an area of the integrated circuit for device performance modification, and modifying a portion of the doped feature layout that corresponds with the identified area of the integrated circuit during a mask preparation process, thereby providing a modified doped feature layout.

摘要翻译： 本公开提供了一种用于在掩模准备期间修改掺杂区域设计布局以调谐设备性能的方法和系统。 一种示例性方法包括接收设计成定义集成电路的集成电路设计布局，其中集成电路设计布局包括掺杂特征布局; 识别用于器件性能修改的集成电路的区域，以及在掩模准备过程期间修改与所识别的集成电路的区域相对应的掺杂特征布局的一部分，从而提供修改的掺杂特征布局。