公开(公告)号：US09343318B2

公开(公告)日：2016-05-17

申请号：US13367989

申请日：2012-02-07

申请人： Mei-Hsuan Lin ,  Chih-Hsun Lin ,  Ching-Hua Chu ,  Ling-Sung Wang

发明人： Mei-Hsuan Lin ,  Chih-Hsun Lin ,  Ching-Hua Chu ,  Ling-Sung Wang

IPC分类号： H01L21/285 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/28518 ,  H01L21/02381 ,  H01L21/02425 ,  H01L21/02532 ,  H01L21/02617 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L29/41783 ,  H01L29/4933 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/7845 ,  H01L29/7848

摘要： A semiconductor device having a source feature and a drain feature formed in a substrate. The semiconductor device having a gate stack over a portion of the source feature and over a portion of the drain feature. The semiconductor device further having a first cap layer formed over substantially the entire source feature not covered by the gate stack, and a second cap layer formed over substantially the entire drain feature not covered by the gate stack. A method of forming a semiconductor device including forming a source feature and drain feature in a substrate. The method further includes forming a gate stack over a portion of the source feature and over a portion of the drain feature. The method further includes depositing a first cap layer over substantially the entire source feature not covered by the gate stack and a second cap layer over substantially the entire drain feature not covered by the gate stack.

摘要翻译： 一种半导体器件，其具有形成在衬底中的源特征和漏极特征。 该半导体器件在源特征的一部分上方并且在漏极特征的一部分上方具有栅极堆叠。 所述半导体器件还具有形成在基本上整个源极特征上的第一覆盖层，其未被所述栅极堆叠覆盖，以及形成在基本上整个漏极特征（未被所述栅极堆叠覆盖）的第二覆盖层。 一种形成半导体器件的方法，包括在衬底中形成源极特征和漏极特征。 该方法还包括在源特征的一部分上并在漏极特征的一部分之上形成栅叠层。 该方法还包括在未被栅极堆叠覆盖的基本上整个源特征上沉积第一盖层，以及在未被栅极堆叠覆盖的基本整个漏极特征上沉积第二盖层。

公开(公告)号：US20130234217A1

公开(公告)日：2013-09-12

申请号：US13415611

申请日：2012-03-08

申请人： Mei-Hsuan Lin ,  Chih-Hsun Lin ,  Ching-Hua Chu ,  Ling-Sung Wang

发明人： Mei-Hsuan Lin ,  Chih-Hsun Lin ,  Ching-Hua Chu ,  Ling-Sung Wang

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/66507 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/02694 ,  H01L21/30604 ,  H01L21/308 ,  H01L29/165 ,  H01L29/41758 ,  H01L29/45 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A device includes a semiconductor substrate, a gate stack over the semiconductor substrate, and a stressor region having at least a portion in the semiconductor substrate and adjacent to the gate stack. The stressor region includes a first stressor region having a first p-type impurity concentration, a second stressor region over the first stressor region, wherein the second stressor region has a second p-type impurity concentration, and a third stressor region over the second stressor region. The third stressor region has a third p-type impurity concentration. The second p-type impurity concentration is lower than the first and the third p-type impurity concentrations.

公开(公告)号：US08994097B2

公开(公告)日：2015-03-31

申请号：US13415611

申请日：2012-03-08

申请人： Mei-Hsuan Lin ,  Chih-Hsun Lin ,  Ching-Hua Chu ,  Ling-Sung Wang

发明人： Mei-Hsuan Lin ,  Chih-Hsun Lin ,  Ching-Hua Chu ,  Ling-Sung Wang

IPC分类号： H01L29/66 ,  H01L29/165 ,  H01L29/78

CPC分类号： H01L29/66507 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/02694 ,  H01L21/30604 ,  H01L21/308 ,  H01L29/165 ,  H01L29/41758 ,  H01L29/45 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A device includes a semiconductor substrate, a gate stack over the semiconductor substrate, and a stressor region having at least a portion in the semiconductor substrate and adjacent to the gate stack. The stressor region includes a first stressor region having a first p-type impurity concentration, a second stressor region over the first stressor region, wherein the second stressor region has a second p-type impurity concentration, and a third stressor region over the second stressor region. The third stressor region has a third p-type impurity concentration. The second p-type impurity concentration is lower than the first and the third p-type impurity concentrations.

摘要翻译： 一种器件包括半导体衬底，半导体衬底上的栅极叠层以及具有至少一部分在半导体衬底中并与栅叠层相邻的应力区。 所述应激源区域包括具有第一p型杂质浓度的第一应激源区域，超过所述第一应激区域的第二应激区域，其中所述第二应激区域具有第二p型杂质浓度，以及所述第二应激源上的第三应力区域 地区。 第三应力区域具有第三p型杂质浓度。 第二种p型杂质浓度低于第一和第三种p型杂质浓度。

公开(公告)号：US5517136A

公开(公告)日：1996-05-14

申请号：US398123

申请日：1995-03-03

申请人： David Harris ,  Sunny C. Huang ,  James Nadir ,  Ching-Hua Chu ,  Jason C. Stinson ,  Alper Ilkbahar

发明人： David Harris ,  Sunny C. Huang ,  James Nadir ,  Ching-Hua Chu ,  Jason C. Stinson ,  Alper Ilkbahar

IPC分类号： H03K19/017 ,  H03K19/096

CPC分类号： H03K19/01728 ,  H03K19/0963

摘要： An opportunistic time-borrowing domino logic includes a domino pipeline having a plurality of logic gates coupled in series and controlled by first, second, third and fourth clock signals. The first domino gate in a half-cycle is clocked by either the first or the second clock signals, wherein the last domino gate in a half-cycle is clocked by either the third or the fourth clock cycles. The second clock signal is an inverse of the first clock signal, and the third and fourth clock signals have local delayed clock phases in which the falling edges of the third and fourth clock signals are delayed relative to the falling edges of the respective first and second clock signals. In a first half-cycle, a first type of domino gate is controlled by the first clock signal, with subsequent domino gates of the same type being controlled by the third clock signal. Odd-numbered half-cycles begin with a domino gate of the second type controlled by the second clock signal, followed by domino gates of the first type controlled by the fourth clock signal.

摘要翻译： 机会时间借用多米诺骨牌包括具有串联耦合并由第一，第二，第三和第四时钟信号控制的多个逻辑门的多米诺河流管线。 半周期中的第一个多米诺骨门由第一或第二时钟信号计时，其中半周期中最后的多米诺门由第三或第四个时钟周期计时。 第二时钟信号是第一时钟信号的倒数，并且第三和第四时钟信号具有本地延迟的时钟相位，其中第三和第四时钟信号的下降沿相对于相应的第一和第二时钟信号的下降沿被延迟 时钟信号。 在第一个半周期中，第一种类型的多米诺式门由第一时钟信号控制，同一类型的后续多米诺式门由第三时钟信号控制。 奇数半周期以由第二时钟信号控制的第二类型的多米诺门开始，其后是由第四时钟信号控制的第一类型的多米诺门。

公开(公告)号：US5479641A

公开(公告)日：1995-12-26

申请号：US35630

申请日：1993-03-24

申请人： James Nadir ,  Ching-Hua Chu

发明人： James Nadir ,  Ching-Hua Chu

IPC分类号： G06F11/10 ,  G06F12/08 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F11/1064 ,  G06F12/0855

摘要： A cache circuit for a computer microprocessor and a method for performing cache operations (e.g., read and write) in a single, short cycle using overlapped clocking. The cache includes a tag array, a status array, and a data array. Parity information is generated and checked to verify data and tag integrity. The parity field is stored in a status array physically separate from the tag array. The status array is offset in timing so that it lags behind the tag array for both read and write operations. Therefore, fields in the status array can be written in the early part of the next clock cycle without affecting the tag array or another operation that may be scheduled for the next time cycle.

摘要翻译： 一种用于计算机微处理器的缓存电路和用于使用重叠时钟在单个短周期中执行高速缓存操作（例如，读和写）的方法。 缓存包括标签数组，状态数组和数据数组。 生成和检查奇偶校验信息以验证数据和标签完整性。 奇偶校验字段存储在与标签数组物理分离的状态数组中。 状态数组在时序上偏移，因此它们在读取和写入操作时滞后于标签数组。 因此，状态数组中的字段可以在下一个时钟周期的早期部分写入，而不会影响标签数组或可能在下一个时间周期内调度的另一个操作。

公开(公告)号：US5737569A

公开(公告)日：1998-04-07

申请号：US622614

申请日：1996-03-26

申请人： James Nadir ,  Ching-Hua Chu

发明人： James Nadir ,  Ching-Hua Chu

IPC分类号： G06F12/08 ,  G06F13/16 ,  G06F12/00 ,  G06F13/14

CPC分类号： G06F12/0853 ,  G06F12/0831 ,  G06F13/1605

摘要： An arbitration circuit and method for a multiport high speed memory in a computer microprocessor. A plurality of addresses are provided to a plurality of ports. The addresses are decoded in a plurality of decoders. The decoded output lines are compared in a comparison circuitry to determine if one or more of the ports is requesting access to the same memory line, and a comparison bit indicative of a match is outputted. If asserted, the comparison bit disables a line driver so that only one of the wordlines in a particular memory line is driven at any one time.

摘要翻译： 一种用于计算机微处理器中的多端口高速存储器的仲裁电路和方法。 多个地址被提供给多个端口。 地址在多个解码器中解码。 解码的输出线在比较电路中进行比较以确定一个或多个端口是否请求访问相同的存储器线，并且输出表示匹配的比较位。 如果断言，比较位将禁用线路驱动程序，以便在任何一个时间只驱动特定存储器线中的一条字线。

公开(公告)号：US5450565A

公开(公告)日：1995-09-12

申请号：US35740

申请日：1993-03-23

申请人： James Nadir ,  Ching-Hua Chu

发明人： James Nadir ,  Ching-Hua Chu

IPC分类号： G06F12/08 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0864

摘要： A set select circuit and method for selecting a set in a set associative cache in a microprocessor. The set select circuit, responsive to a main clock, includes an input latch coupled to receive select data before the main clock cycle. The input latch is transparent to set select data so that predecoding can begin before the main clock. The input latch latches the set select data on the initial clock edge and holds the set select data during the first half of the main clock cycle. A pre-decoder is coupled to the input latch for receiving and predecoding the set select data, and a decoder is coupled to the predecoder for receiving and decoding the pre-decoded set select data to supply an output to an output latch. The output latch is also coupled to a clock inverter to receive the inverted delayed clock signal. The output latch is transparent during the second half of an inverted delayed clock cycle. The output latch latches the selected set on the initial inverted delayed clock edge and holds the selected set during the first half of the inverted delayed clock cycle.

摘要翻译： 一种用于在微处理器中选择集合相关高速缓存中的集合的集合选择电路和方法。 响应于主时钟的设定选择电路包括耦合以在主时钟周期之前接收选择数据的输入锁存器。 输入锁存器是透明的，用于设置选择数据，以便预编码可以在主时钟之前开始。 输入锁存器锁存初始时钟沿上的置1选择数据，并在主时钟周期的前半部分保持置位选择数据。 预解码器耦合到输入锁存器，用于接收和预编码集合选择数据，并且解码器耦合到预解码器，用于接收和解码预解码集合选择数据以向输出锁存器提供输出。 输出锁存器还耦合到时钟反相器以接收反相延迟的时钟信号。 在反相延迟时钟周期的后半期间，输出锁存器是透明的。 输出锁存器在初始反相延迟时钟沿锁存所选择的集合，并且在反相延迟时钟周期的前一半期间保持所选择的集合。

公开(公告)号：US20070087544A1

公开(公告)日：2007-04-19

申请号：US11252764

申请日：2005-10-19

申请人： Hsu-Liang Chang ,  Ching-Hua Chu

发明人： Hsu-Liang Chang ,  Ching-Hua Chu

IPC分类号： H01L21/44

CPC分类号： H01L24/05 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/1147 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/05552

摘要： Methods for forming an improved bump structure on a semiconductor device are provided. In one embodiment, a substrate is provided having at least one contact pad formed thereon. A first passivation layer is formed over the substrate, the first passivation layer having at least one opening therein exposing a portion of the contact pad. A first patterned and etched conductive metal layer is formed on the contact pad and above a portion of the first passivation layer. A second patterned and etched passivation layer is formed above the first passivation layer and a portion of the first conductive metal layer, wherein a portion of the ends of the first conductive metal layer is wedged between the first and second passivation layers. A second conductive metal layer is formed above the second passivation layer and the first conductive metal layer. A patterned and etched photoresist layer is then formed over a portion of the second passivation layer, the photoresist layer having an opening overlying the contact pad, and a solder material is deposited in the opening to form a solder column. The photoresist layer is thereafter removed and the second conductive metal layer is etched to the second passivation layer by using the solder column as an etching mask. The solder column is then reflown to create a solder bump.

摘要翻译： 提供了在半导体器件上形成改进的凸块结构的方法。 在一个实施例中，提供具有形成在其上的至少一个接触垫的基板。 第一钝化层形成在衬底上，第一钝化层具有至少一个开口，露出接触焊盘的一部分。 第一图案化和蚀刻的导电金属层形成在接触焊盘上并在第一钝化层的一部分上方。 第一图案化和蚀刻钝化层形成在第一钝化层上方和第一导电金属层的一部分上，其中第一导电金属层的端部的一部分楔入第一和第二钝化层之间。 第二导电金属层形成在第二钝化层和第一导电金属层之上。 然后在第二钝化层的一部分上形成图案化和蚀刻的光致抗蚀剂层，光致抗蚀剂层具有覆盖接触焊盘的开口，并且焊料材料沉积在开口中以形成焊料柱。 然后通过使用焊料柱作为蚀刻掩模，去除光致抗蚀剂层，并将第二导电金属层蚀刻到第二钝化层。 焊料柱然后被重新熔化以产生焊料凸块。