公开(公告)号：US5970356A

公开(公告)日：1999-10-19

申请号：US237884

申请日：1999-01-27

申请人： Chang-ki Jeon

发明人： Chang-ki Jeon

IPC分类号： H01L29/73 ,  H01L21/285 ,  H01L21/331 ,  H01L21/763 ,  H01L29/08 ,  H01L29/732

CPC分类号： H01L29/66272 ,  H01L21/28512 ,  H01L21/763 ,  H01L29/0821 ,  H01L29/7322

摘要： A bipolar transistor and a method of fabricating the same are provided which are adapted to reduce chip size and production costs. To produce the transistor, a second conductive type well region is formed in a first conductive type semiconductor substrate and isolation trenches are formed at both sides of the well region. A high density second conductive type buried layer is formed in the semiconductor substrate which is formed at the bottom of the isolation trench. The buried layer is formed in two regions surrounding respective bottoms of two adjacent isolation trenches. The two regions are electrically connected with each other and in direct contact with the well region. An extrinsic base region and a device isolation region are formed sequentially onto the semiconductor substrate using a nitration layer pattern as a mask, wherein the nitration layer pattern is formed on the surface of semiconductor substrate. An intrinsic base region is formed into the well region and an emitter region into the intrinsic base region using the device isolation layer as a mask. The bipolar transistor and method of fabrication can reduce the chip size, the production costs, and the resistance of the collector by forming the isolation trench, wherein the isolation trench is used to form the buried layer and functions as a sink layer (collector layer). The process provides self-alignment of the extrinsic base region, the intrinsic base region, and the emitter region to reduce process scattering.

摘要翻译： 提供了双极晶体管及其制造方法，其适于减小芯片尺寸和生产成本。 为了制造晶体管，在第一导电型半导体衬底中形成第二导电类型阱区，并且在阱区的两侧形成隔离沟槽。 在形成在隔离沟槽的底部的半导体衬底中形成高密度第二导电型掩埋层。 掩埋层形成在两个相邻隔离沟槽的相应底部周围的两个区域中。 两个区域彼此电连接并且与阱区域直接接触。 使用硝化层图案作为掩模，在半导体衬底上顺序地形成非本征基区和器件隔离区，其中在半导体衬底的表面上形成硝化层图案。 使用器件隔离层作为掩模，将本征基极区域形成为阱区域和发射极区域到本征基极区域。 双极晶体管和制造方法可以通过形成隔离沟槽来减小芯片尺寸，生产成本和集电极的电阻，其中隔离沟槽用于形成埋层并用作沉积层（集电极层） 。 该方法提供外部碱性区域，本征碱基区域和发射极区域的自对准，以减少工艺散射。

公开(公告)号：US07888768B2

公开(公告)日：2011-02-15

申请号：US11329268

申请日：2006-01-09

申请人： Sung-lyong Kim ,  Chang-ki Jeon ,  Jong-jib Kim ,  Jong-tae Hwang

发明人： Sung-lyong Kim ,  Chang-ki Jeon ,  Jong-jib Kim ,  Jong-tae Hwang

IPC分类号： H01L21/70 ,  H01L21/77

CPC分类号： H01L29/808 ,  H01L27/088

摘要： In one embodiment, a power integrated circuit device is provided. The power integrated circuit device includes a high-side power switch having a high voltage transistor and a low voltage transistor. The high voltage transistor has a gate, a source, and a drain, and is capable of withstanding a high voltage applied to its drain. The low voltage transistor has a gate, a source, and a drain, wherein the drain of the low voltage transistor is connected to the source of the high voltage transistor and the source of the low voltage transistor is connected to the gate of the high voltage transistor, and wherein a control signal is applied to the gate of the low voltage transistor from the power integrated circuit device. The high-side power switch is turned on when a predetermined voltage is applied to the source of the low voltage transistor, a voltage higher than the predetermined voltage is applied to the drain of the high voltage transistor, and a voltage level of the control signal becomes higher than the predetermined voltage by a threshold voltage of the low voltage transistor.

摘要翻译： 在一个实施例中，提供了功率集成电路器件。 功率集成电路装置包括具有高压晶体管和低压晶体管的高侧电源开关。 高压晶体管具有栅极，源极和漏极，并且能够承受施加到其漏极的高电压。 低压晶体管具有栅极，源极和漏极，其中低压晶体管的漏极连接到高压晶体管的源极，并且低压晶体管的源极连接到高电压的栅极 晶体管，并且其中控制信号从功率集成电路器件施加到低电压晶体管的栅极。 当向低电压晶体管的源极施加预定电压时，高侧电源开关接通，将高于预定电压的电压施加到高电压晶体管的漏极，并且控制信号的电压电平 通过低压晶体管的阈值电压变得高于预定电压。

公开(公告)号：US07777524B2

公开(公告)日：2010-08-17

申请号：US12402528

申请日：2009-03-12

申请人： Chang-ki Jeon ,  Min-suk Kim ,  Yong-cheol Choi

发明人： Chang-ki Jeon ,  Min-suk Kim ,  Yong-cheol Choi

IPC分类号： H03K19/0175

CPC分类号： H01L27/088 ,  H01L21/823481

摘要： Provided are a high-voltage semiconductor device including a junction termination which electrically isolates a low voltage unit from a high voltage unit, and a method of fabricating the same. The high voltage semiconductor device includes a high voltage unit, a low voltage unit surrounding the high voltage unit, and a junction termination formed between the high voltage unit and the low voltage unit and surrounding the high voltage unit to electrically isolate the high voltage unit from the low voltage unit. The junction termination includes at least one level shifter which level shifts signals from the low voltage unit and supplies the same to the high voltage unit, a first device isolation region surrounding the high voltage unit to electrically isolate the high voltage unit from the level shifter, and a resistor layer electrically connecting neighboring level shifters.

摘要翻译： 提供一种包括将低电压单元与高电压单元电隔离的接合端子的高压半导体器件及其制造方法。 高电压半导体器件包括高电压单元，围绕高电压单元的低电压单元，以及形成在高电压单元和低电压单元之间并且围绕高电压单元的连接端子，以将高压单元与 低压单位。 所述连接终端包括至少一个电平移位器，其将来自所述低电压单元的信号电平移位并将其提供给所述高压单元;围绕所述高压单元的第一器件隔离区，以将所述高压单元与所述电平移位器电隔离; 以及电连接相邻电平移位器的电阻层。

公开(公告)号：US20090166797A1

公开(公告)日：2009-07-02

申请号：US12397426

申请日：2009-03-04

申请人： Sung-Iyong Kim ,  Chang-ki Jeon

发明人： Sung-Iyong Kim ,  Chang-ki Jeon

IPC分类号： H01L27/06 ,  H01L29/93 ,  H01L23/58

CPC分类号： H01L29/8611 ,  H01L27/0629 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/868 ,  H01L2924/0002 ,  H03K17/6877 ,  H03K2217/0036 ,  H01L2924/00

摘要： Provided is a high-voltage integrated circuit device including a high-voltage resistant diode. The device includes a low-voltage circuit region having a plurality of semiconductor devices, which operate with respect to a ground voltage, a high-voltage circuit region having a plurality of semiconductor devices, which operate with respect to a voltage that varies from the ground voltage to a high voltage, a junction termination and a first isolation region electrically isolating the low-voltage circuit region from the high-voltage circuit region, a high-voltage resistant diode formed between the low-voltage circuit region and the high-voltage circuit region, and a second isolation region surrounding the high-voltage resistant diode and electrically isolating the high-voltage resistant diode from the low-voltage circuit region and the high-voltage circuit region. Therefore, a leakage current of the high-voltage resistant diode can be prevented.

摘要翻译： 提供一种包括耐高压二极管的高压集成电路装置。 该器件包括具有多个相对于接地电压工作的多个半导体器件的低电压电路区域，具有多个半导体器件的高电压电路区域，其相对于从地面变化的电压工作 电压到高电压，接合端接和将低压电路区域与高压电路区域电隔离的第一隔离区域，形成在低压电路区域和高压电路之间的高耐压二极管 以及围绕所述耐高压二极管的第二隔离区域，并且将所述耐高压二极管与所述低压电路区域和所述高压电路区域电隔离。 因此，可以防止高耐压二极管的漏电流。

公开(公告)号：US20080001198A1

公开(公告)日：2008-01-03

申请号：US11479149

申请日：2006-06-29

申请人： Chang-ki Jeon ,  Gary Dolny

发明人： Chang-ki Jeon ,  Gary Dolny

IPC分类号： H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L29/7825 ,  H01L29/0634 ,  H01L29/0696

摘要： A field effect transistor includes a trench gate extending into a semiconductor region. The trench gate has a front wall facing a drain region and a side wall perpendicular to the front wall. A channel region extends along the side wall of the trench gate, and a drift region extends at least between the drain region and the trench gate. The drift region includes a stack of alternating conductivity type silicon layers.

摘要翻译： 场效应晶体管包括延伸到半导体区域中的沟槽栅极。 沟槽门具有面向漏区的前壁和垂直于前壁的侧壁。 沟道区域沿着沟槽栅极的侧壁延伸，并且漂移区域至少在漏极区域和沟槽栅极之间延伸。 漂移区域包括一叠交替导电型硅层。

公开(公告)号：US20070264785A1

公开(公告)日：2007-11-15

申请号：US11828128

申请日：2007-07-25

申请人： Yong-cheol Choi ,  Chang-ki Jeon ,  Cheol-joong Kim

发明人： Yong-cheol Choi ,  Chang-ki Jeon ,  Cheol-joong Kim

IPC分类号： H01L27/085

CPC分类号： H01L29/66674 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/7816

摘要： A method of forming a metal oxide semiconductor (MOS) transistor includes the following steps. A substrate of a first conductivity is provided. A first buried layer of a second conductivity type is formed over the substrate. A second buried layer of the first conductivity type is formed in the first buried layer. An epitaxial layer of the second conductivity type is formed over the substrate. A drift region of a second conductivity type is formed in the epitaxial layer. A gate layer is formed over the drift region. A body region of the first conductivity type is formed in the drift region such that the gate overlaps a surface portion of the body region. A source region of the second conductivity is formed in the body region. A drain region of the second conductivity type is formed in the drift region. The drain region is laterally spaced from the body region. The first and second buried layers laterally extend from under the body region to under the drain region. The surface portion of the body region extends between the source region and the drift region to form a channel region of the transistor.

摘要翻译： 形成金属氧化物半导体（MOS）晶体管的方法包括以下步骤。 提供第一导电性的衬底。 在衬底上形成第二导电类型的第一掩埋层。 第一导电类型的第二掩埋层形成在第一掩埋层中。 在衬底上形成第二导电类型的外延层。 在外延层中形成第二导电类型的漂移区。 在漂移区上形成栅极层。 第一导电类型的体区形成在漂移区域中，使得栅极与身体区域的表面部分重叠。 在身体区域中形成第二导电性的源极区域。 在漂移区域中形成第二导电类型的漏极区域。 漏极区域与身体区域横向间隔开。 第一和第二掩埋层从身体区域下方横向延伸到漏极区域下方。 体区域的表面部分在源极区域和漂移区域之间延伸以形成晶体管的沟道区域。

公开(公告)号：US06888210B2

公开(公告)日：2005-05-03

申请号：US10360518

申请日：2003-02-07

申请人： Chang-ki Jeon ,  Min-hwan Kim ,  Sung-lyong Kim

发明人： Chang-ki Jeon ,  Min-hwan Kim ,  Sung-lyong Kim

IPC分类号： H01L29/772 ,  H01L21/266 ,  H01L21/336 ,  H01L21/74 ,  H01L23/58 ,  H01L29/08 ,  H01L29/10 ,  H01L29/76 ,  H01L29/78 ,  H01L29/94 ,  H01L31/0328 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/7816 ,  H01L21/266 ,  H01L21/74 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66674 ,  H01L29/7835

摘要： In accordance with the present invention, a metal oxide semiconductor (MOS) transistor has a substrate of a first conductivity type. A drift region of a second conductivity type is formed over the substrate. A body region of the first conductivity type is formed in the drift region. A source region of the second conductivity is formed in the body region. A gate extends over a surface portion of the body region and overlaps each of the source region and the body region such that the surface portion of the body region forms a channel region of the transistor. A drain region of the second conductivity type is formed in the drift region. The drain region is laterally spaced from the source region a first predetermined distance. A first buried layer of the first conductivity type extends into the substrate and the drift region. The first buried layer laterally extends between the source and drain regions.

摘要翻译： 根据本发明，金属氧化物半导体（MOS）晶体管具有第一导电类型的衬底。 在衬底上形成第二导电类型的漂移区。 在漂移区域中形成第一导电类型的体区。 在身体区域中形成第二导电性的源极区域。 栅极延伸在主体区域的表面部分上并且与源区域和主体区域中的每一个重叠，使得主体区域的表面部分形成晶体管的沟道区域。 在漂移区域中形成第二导电类型的漏极区域。 漏极区域与源极区域在第一预定距离上横向间隔开。 第一导电类型的第一掩埋层延伸到衬底和漂移区域中。 第一掩埋层在源区和漏区之间横向延伸。

公开(公告)号：US06833585B2

公开(公告)日：2004-12-21

申请号：US10120207

申请日：2002-04-10

申请人： Min-hwan Kim ,  Chang-ki Jeon ,  Young-suk Choi

发明人： Min-hwan Kim ,  Chang-ki Jeon ,  Young-suk Choi

IPC分类号： H01L2976

CPC分类号： H01L29/7816 ,  H01L29/0634 ,  H01L29/7835

摘要： A high voltage lateral Double diffused Metal Oxide Semiconductor (DMOS) transistor includes a plurality of well regions of a first conductivity type formed to be spaced out within a well region of a second conductivity type between a channel region of the first conductivity type and a drain region of the second conductivity type. Most current is carried through some portions of the well region of the second conductivity type in which the well regions of the first conductivity do not appear so that the current carrying performance of the device is improved. When a bias voltage is applied to the drain region, the well region of the second conductivity type is completely depleted at other portions where the well region of the second conductivity type and the well regions of the first conductivity type alternately appear so that the breakdown voltage of the device can be increased. In addition, since the well region of the second conductivity type can be easily depleted, not only the breakdown voltage can be increased, but also the impurity concentration of the well region of the second conductivity type can be increased. Accordingly, the on-resistance of the device can be decreased.

摘要翻译： 高压横向双扩散金属氧化物半导体（DMOS）晶体管包括多个第一导电类型的阱区，其形成为在第一导电类型的沟道区域和漏极之间的第二导电类型的阱区域内间隔开 第二导电类型的区域。 大多数电流通过第二导电类型的阱区的一些部分被携带，其中第一导电性的阱区不出现，从而提高了器件的载流性能。 当偏置电压施加到漏极区域时，第二导电类型的阱区域在第二导电类型的阱区域和第一导电类型的阱区域交替出现的其它部分完全耗尽，使得击穿电压 的设备可以增加。 此外，由于第二导电类型的阱区域容易耗尽，不仅可以提高击穿电压，而且能够提高第二导电型阱区的杂质浓度。 因此，可以降低器件的导通电阻。