公开(公告)号：US11417642B2

公开(公告)日：2022-08-16

申请号：US17006378

申请日：2020-08-28

Applicant: KIOXIA CORPORATION

Inventor： Tomoya Sanuki ,  Toshio Fujisawa ,  Hiroshi Maejima ,  Takashi Maeda

IPC: G11C16/04 ,  H01L25/18 ,  H01L23/00 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G06F3/06

Abstract: A semiconductor storage device includes a plurality of memory chips and a circuit chip. The plurality of memory chips and the circuit chip are stacked on each other. Each of the plurality of memory chips has a memory cell array that includes a plurality of memory cells. The circuit chip includes a data latch configured to store page data for writing or reading data into or from the memory cell array of each of the memory chips.

公开(公告)号：US12211567B2

公开(公告)日：2025-01-28

申请号：US17816836

申请日：2022-08-02

Applicant: Kioxia Corporation

Inventor： Kazutaka Ikegami ,  Takashi Maeda ,  Reiko Sumi

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

Abstract: A memory system according to an embodiment includes a first bit line, a source line, a first word line, a second word line, a first memory pillar and a control circuit. The control circuit performs a first verify operation to first and second memory cells, a second verify operation to the first memory cell, a third verify operation to the second memory cell and a write operation or a read operation with a lower voltage in accordance with a request from an external device.

公开(公告)号：US11908525B2

公开(公告)日：2024-02-20

申请号：US17340310

申请日：2021-06-07

Applicant: Kioxia Corporation

Inventor： Takashi Maeda

IPC: G11C16/04 ,  G11C16/16 ,  G11C16/08 ,  H10B43/27 ,  H10B43/35 ,  G11C16/14 ,  G11C16/26 ,  G11C16/10 ,  G11C5/14 ,  G11C16/30

CPC classification number: G11C16/16 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H10B43/27 ,  H10B43/35 ,  G11C5/145 ,  G11C16/30

Abstract: When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.

公开(公告)号：US11538791B2

公开(公告)日：2022-12-27

申请号：US16802462

申请日：2020-02-26

Applicant: KIOXIA CORPORATION

Inventor： Hiroshi Maejima ,  Toshifumi Hashimoto ,  Takashi Maeda ,  Masumi Saitoh ,  Tetsuaki Utsumi

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: A semiconductor memory device includes a memory chip. The memory chip includes a first region including a plurality of first memory cells and second memory cells, a second region different from the first region, a plurality of first word lines stacked apart from each other in a first direction in the first and second regions, a first pillar including a first semiconductor layer extending through the first word lines, and a first insulator layer provided between the first semiconductor layer and the first word lines, in the first region, the first memory cells being located at intersections of the first pillar with the first word lines, a first bonding pad in the second region, and a first transistor between the first word lines and the first bonding pad, and connected between one of the first word lines and the first bonding pad, in the second region.

公开(公告)号：US11322212B2

公开(公告)日：2022-05-03

申请号：US17014695

申请日：2020-09-08

Applicant: KIOXIA CORPORATION

Inventor： Takashi Maeda

IPC: G11C11/22 ,  G11C16/34 ,  G11C16/16 ,  G11C16/12 ,  G11C11/56 ,  G11C16/04 ,  G11C5/14 ,  G11C7/10 ,  G11C7/06

Abstract: A semiconductor memory device according to an embodiment includes a string, a bit line, a well line, and a sequencer. The string includes first and second select transistors, and memory cell transistors using a ferroelectric material. The bit line and the well line are connected to the first and second select transistors, respectively. At a time in an erase verify operation, the sequencer is configured to apply a first voltage to the memory cell transistors, to apply a second voltage lower than the first voltage to the first select transistor, to apply a third voltage lower than the first voltage to the second select transistor, to apply a fourth voltage to the bit line, and to apply a fifth voltage higher than the fourth voltage to the well line.

公开(公告)号：US11139037B2

公开(公告)日：2021-10-05

申请号：US16783782

申请日：2020-02-06

Applicant: KIOXIA CORPORATION

Inventor： Takashi Maeda

IPC: G11C16/34 ,  G11C5/06 ,  H01L27/11582 ,  H01L27/11556 ,  G11C16/26

Abstract: According to one embodiment, a semiconductor memory device includes: a first memory cell and a second memory cell capable of storing data and coupled in parallel to a bit line; a first word line coupled to the first memory cell; a second word line coupled to the second memory cell and being different from the first word line; and a control circuit. The first memory cell and the second memory cell share a first well region and are opposed to each other, with the first well region interposed. The control circuit is configured, in a first operation, to repeat application of a first voltage to the first word line and the second word line a plurality of times while increasing the first voltage.